Delay Circuit Test Using Clock Pulse Counting for At-Speed Coverage
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Solution Overview
Problem
Conventional delay chain circuits are unable to perform high-speed tests due to the long overall time delay caused by multiple delay cells, resulting in incomplete testing and potential defects going undetected until after packaging.
Innovation Solution
A test method and circuitry that includes an additional clock pulse generator and counter to enable high-speed testing by generating and counting clock signals, allowing for the evaluation of all delay cells and ensuring complete testing before packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple delay cells are used in the delay chain circuit to control signal delay, then the delay control capability is improved, but the overall time delay increases causing inability to perform high-speed tests
Solution Approach 1:
The delay chain circuit is divided into multiple individual delay cells (first delay cell, second delay cell, third delay cell, etc.) that can be independently controlled. Each delay cell can be selectively enabled or disabled through separate control signals, allowing the system to achieve variable delay control without requiring all cells to be active simultaneously, thus reducing the overall time delay when full delay is not needed.
Solution Approach 2:
The delay chain circuit incorporates dynamic control mechanisms where the delay path can be flexibly adjusted based on test requirements. Control logic selectively activates specific delay cells to create different delay configurations, enabling the circuit to adapt between long delay modes (for low-speed testing) and short delay modes (for high-speed testing), resolving the contradiction between delay control capability and testing speed.
2Reliability
If the delay chain circuit is configured for low-speed scan test, then the test coverage is improved, but the test speed decreases causing gap with actual clock rate
Solution Approach 1:
The delay chain circuit is designed with dynamic reconfiguration capability that allows switching between different operational modes. For comprehensive testing, all delay cells can be activated to provide maximum delay control for thorough scan test coverage. For speed-critical testing, the circuit can be reconfigured to minimize delay, enabling tests to run at or near actual clock rates (e.g., 800 MHz), thus eliminating the gap between test speed and operational speed while maintaining test effectiveness.
Solution Approach 2:
The circuit allows changing the delay parameter dynamically based on test requirements. By adjusting which delay cells are active and configuring the delay control logic appropriately, the system can optimize the delay parameter to match the desired test speed, enabling both slow comprehensive scans and fast at-speed tests without sacrificing coverage.
3Speed
If functional test is used to test high-speed signals, then the test speed is improved, but the testing cannot be performed on all delay cells effectively
Solution Approach 1:
The delay chain circuit is designed with multi-functionality to serve both comprehensive scan test purposes and high-speed functional test purposes. The same physical circuit structure can be configured to enable complete coverage of all delay cells during scan tests, and then reconfigured to operate at high speeds during functional tests, making a single circuit serve multiple testing functions effectively.
Solution Approach 2:
Before performing high-speed functional tests, the delay chain circuit can be preliminarily configured and validated using scan test mode to ensure all delay cells are functioning correctly. This preliminary action ensures complete testing of the delay infrastructure before switching to high-speed operational testing, guaranteeing both completeness and speed in the overall test process.
Data Source
AI summary
A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.