Real-Time Clock Module Data Verification for Timing Reliability

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Solution Overview

Problem

Existing real-time clock devices cannot detect abnormalities in adjustment data used for oscillation frequency adjustments, which can affect the reliability of timing data.

Innovation Solution

A real-time clock module with a data abnormality determination circuit that compares first and second data to detect abnormalities, using flag registers to indicate normal or abnormal conditions, and a time register to capture time information when abnormalities occur.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If adjustment data is stored and used for oscillation frequency adjustment, then the oscillation frequency can be adjusted to compensate for temperature drift and other factors, but the reliability of timing data cannot be ensured because abnormalities in the adjustment data cannot be detected

Engineering Contradiction:
Improvereliability of timing dataVSAvoidcomplexity of data verification system
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-storing verification data (identical copies of adjustment data) in a storage unit before the data is actually used for oscillation frequency adjustment. This verification data is then compared with the adjustment data after loading to detect any abnormalities. By preparing the verification data in advance, the system can perform reliability checks without adding significant operational complexity, thus improving timing data reliability while maintaining acceptable device complexity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If verification data is stored and compared to detect abnormalities, then the reliability of timing data is improved, but the device complexity increases due to additional storage and comparison circuits

Engineering Contradiction:
Improvedetection of data abnormalitiesVSAvoidcomplexity of storage and comparison system
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies the copying principle by creating an exact duplicate of the adjustment data and storing it in a storage unit as verification data. This copy is then compared with the original adjustment data after it is loaded into registers. The copying approach allows for simple and direct comparison using basic digital logic circuits, achieving reliable abnormality detection without requiring complex verification algorithms or additional processing systems.

Inventive Principle:
Principle #26Copying

3Reliability

If adjustment data is loaded into registers for comparison, then the data can be verified for abnormalities, but the timing data may be affected by power supply voltage drops during the loading process

Engineering Contradiction:
Improvedata verification capabilityVSAvoidpower supply voltage drop impact
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies beforehand cushioning by designing the system to complete the entire data loading and verification process as a unified operation that occurs before the adjustment data is actually used for oscillation frequency adjustment. The comparison is performed immediately after loading, and only after verification succeeds does the system proceed with using the data. This approach cushions against power supply voltage drops by ensuring that the critical verification step is completed before any timing-critical operations begin, preventing voltage fluctuations from affecting the integrity of the adjustment process.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11543451B2Real-time clock module, electronic device and vehicle
Publication Date: 2023.01.03 SEIKO EPSON CORP
  • US11543451B2 patent drawing
  • US11543451B2 patent drawing
  • US11543451B2 patent drawing

AI summary

A real-time clock module includes an oscillation circuit, a storage unit that stores adjustment data used to adjust an oscillation frequency of the oscillation circuit, a data abnormality determination circuit that compares first data based on the adjustment data with second data based on the adjustment data to determine whether or not at least one of the first data and the second data is abnormal, and a flag register that holds a data abnormality flag in which a first value indicating that the first data and the second data are normal, or a second value indicating that at least one of the first data and the second data is abnormal is set, based on a signal from the data abnormality determination circuit.