Clock Phase Detection Circuit Resilient to Filtered High-Frequency Pulses
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Solution Overview
Problem
Traditional phase detection circuits are unreliable when detecting phase information between high frequency and low frequency clock signals due to potential filtering of high frequency pulses, leading to incorrect detection results.
Innovation Solution
A detection circuit and method that generates a to-be-sampled signal from a low frequency clock signal at the edge of a high frequency clock signal, using a signal generation module and a sampling module to produce a target sampling signal when the high frequency clock is at a preset level and the low frequency clock meets a preset condition, ensuring accurate detection regardless of pulse filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If frequency division is performed on high frequency clock signal for phase detection, then phase detection function for different frequencies is implemented, but detection reliability deteriorates due to potential filtering of high frequency pulses
Solution Approach 1:
The patent applies preliminary action by generating the to-be-sampled signal from the low frequency clock signal before the high frequency clock signal edges arrive. This ensures that the sampling signal is ready and stable before the critical sampling moment, preventing detection errors that would occur if the signal were generated after filtering or during the sampling process itself.
Solution Approach 2:
The patent introduces an intermediary approach by using the low frequency clock signal to generate the to-be-sampled signal, which then serves as the basis for phase detection. This intermediary signal generation method bypasses the reliability issue of directly using high frequency clock signals that may be filtered, while still enabling accurate phase detection between the two different frequency signals.
2Adaptability or versatility
If traditional phase detection method is used for high frequency and low frequency clock signals, then frequency division is required, but detection accuracy deteriorates when the first pulse is filtered out
Solution Approach 1:
The patent generates the to-be-sampled signal in advance using the low frequency clock signal, ensuring that the signal is stable and ready before the high frequency sampling edges arrive. This preliminary signal generation prevents accuracy loss that would occur if the signal were generated after pulse filtering or during the critical sampling window.
Solution Approach 2:
The patent utilizes the periodic nature of clock signals by aligning the generation of the to-be-sampled signal with the periodic edges of the high frequency clock signal. The signal generation is synchronized to occur during specific periodic windows when the high frequency clock is at predetermined levels, ensuring consistent and accurate phase detection across multiple cycles even when individual pulses may be filtered.
Data Source
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AI summary
Provided are a detection circuit and a detection method. The detection circuit is configured to detect phase information between two clock signals of different frequencies, and the two clock signals include a low frequency clock signal and a high frequency clock signal. The detection circuit includes: a signal generation module, configured to detect the low frequency clock signal at an edge of the high frequency clock signal to generate a to-be-sampled signal, and generate a target sampling signal when the high frequency clock signal is kept at a preset level and the low frequency clock signal meets a preset condition; and a sampling module, connected with the signal generation module and configured to detect the to-be-sampled signal at an edge of the target sampling signal to generate a detection result signal.