Dual-Edge Clock Gating With Phased Latches to Avoid Missed Transitions
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Solution Overview
Problem
Conventional clock gating techniques are ineffective for dual-edge-triggered flip-flops, leading to latency and data misses due to inadequate handling of rising and falling edges, which limits their application in digital circuits.
Innovation Solution
A clock gating system comprising digital logic circuits and latch circuits that generate a gated clock signal in-phase or 180 degrees out-of-phase with the input clock signal, ensuring timely activation on both rising and falling edges, thereby controlling dual-edge-triggered flip-flops without missing transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clock gating circuits are used with positive-edge-triggered flip-flops, then power consumption is reduced, but latency and data misses occur in dual-edge-triggered flip-flop applications
Solution Approach 1:
The clock gating circuit is segmented into two separate paths: one path (first digital logic circuit 210) handles rising edges by generating gated clock signals in-phase with the input clock, while the other path (second digital logic circuit 220) handles falling edges by generating gated clock signals 180 degrees out-of-phase. This segmentation allows each path to be optimized for its specific edge type, eliminating the latency and data misses that occur when a single conventional clock gating circuit is used for both edges.
2Loss of energy
If conventional clock gating circuits are used with negative-edge-triggered flip-flops, then power consumption is reduced, but latency and data misses occur in dual-edge-triggered flip-flop applications
Solution Approach 1:
The circuit performs preliminary action by generating the appropriate phased gated clock signal in advance of the flip-flop triggering event. The first digital logic circuit 210 prepares in-phase gated clock signals for rising edge triggers, while the second digital logic circuit 220 prepares 180-degree out-of-phase gated clock signals for falling edge triggers. This preliminary preparation ensures that the correctly phased clock signal is ready before the flip-flop needs to trigger, eliminating latency.
3Device complexity
If a single-phase gated clock signal is used, then circuit complexity is reduced, but transitions on one edge are missed in dual-edge-triggered applications
Solution Approach 1:
The circuit dynamically selects between two different phased gated clock signals based on the edge type detected. The control logic 205 determines whether a rising edge or falling edge is detected and dynamically routes the appropriate phased signal (in-phase from first digital logic circuit 210 or 180-degree out-of-phase from second digital logic circuit 220) to the dual-edge-triggered flip-flop. This dynamic adaptation ensures both edges are captured without missing transitions, maintaining full throughput.
Data Source
AI summary
Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.