Reset Circuit Self-Test for Combined Reset Signal Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In complex processing systems like microcontrollers, ensuring proper reset functionality is critical for safety, but existing systems often fail to verify the correct operation of reset circuits, leading to potential malfunctions and missed resets, which can be catastrophic in safety-critical applications like automotive systems.
Innovation Solution
A processing system with a reset circuit that generates a combined reset-request signal by combining various reset-request signals and includes a test circuit to verify the operation of the reset circuit, ensuring proper reset signal propagation and connectivity, thereby preventing malfunctions and ensuring compliance with safety standards like ASIL-D of the ISO26262 specification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset circuit is added to generate combined reset-request signals, then system reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple individual reset-request signals into a single combined reset-request signal through a reset circuit. This merging approach ensures that if any individual reset request is generated, the combined signal will trigger a system reset, thereby improving reliability without requiring separate verification circuits for each individual reset signal.
Solution Approach 2:
The test circuit is integrated within the processing system itself, allowing the system to automatically verify its own reset circuit functionality. The test circuit generates test reset-request signals and verifies whether the combined reset-request signal is correctly generated, eliminating the need for external verification equipment and reducing overall system complexity.
2Measurement precision
If a test circuit is integrated to verify reset circuit operation, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The processing system includes an integrated test circuit that automatically verifies the functionality of its own reset circuit. The test circuit generates test reset-request signals and checks whether the combined reset-request signal is correctly produced, enabling self-verification without external equipment. This approach achieves precise measurement of reset circuit operation while avoiding the complexity of separate external testing systems.
Solution Approach 2:
The test circuit serves multiple functions: it generates test reset-request signals, verifies the reset circuit operation, and can be integrated with existing system components. By making the test circuit multi-functional and integrating it with the processing system, the patent achieves precise verification capability while minimizing the increase in device complexity.
3Reliability
If multiple reset-request signals are combined, then system safety is improved, but difficulty of detecting and measuring increases
Solution Approach 1:
The reset circuit acts as an intermediary component that receives multiple individual reset-request signals and produces a combined reset-request signal. This intermediary structure simplifies the detection and measurement process by providing a single observable output (the combined signal) that reflects the state of all input signals, making it easier to verify reset signal propagation without needing to individually monitor each input signal path.
Data Source
AI summary
In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.