On-Chip Superconductive IC Testing for Internal Node Observability
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Solution Overview
Problem
Existing DFT techniques for superconductive IC devices are inadequate in providing controllability and observability to detect defects and faults, thereby limiting fault coverage and reliability.
Innovation Solution
The implementation of custom DFT techniques that include test insertion, test extraction, and hybrid test circuitries specifically designed for superconductive IC devices, enhancing controllability and observability of internal nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing DFT techniques are used for superconductive IC devices, then the basic testing functionality is provided, but controllability and observability of internal nodes are insufficient, limiting fault coverage
Solution Approach 1:
The test circuitry is segmented into distinct functional blocks: test insertion circuitry with multiple independent test signal sources, test extraction circuitry with separate observation points, and control logic that independently manages each segment. This modular segmentation enables targeted testing of specific circuit regions while maintaining overall system reliability without requiring complete circuit restructuring.
Solution Approach 2:
Intermediate test nodes and buffer circuits are introduced between the primary test signals and the internal circuit nodes. These intermediary elements provide signal conditioning, level shifting, and isolation functions that enhance the controllability of internal nodes without directly modifying the core superconductive logic circuits, thereby improving fault coverage while limiting complexity propagation.
2Difficulty of detecting and measuring
If test circuitry is added to improve controllability and observability, then fault detection capability is enhanced, but the device complexity and overhead increase
Solution Approach 1:
The test circuitry is designed with multi-functional elements that serve both testing and operational functions. For example, certain circuit nodes serve as both functional signal paths during normal operation and as test observation points during testing. Control logic elements can switch between test mode and operational mode, allowing the same hardware to fulfill multiple purposes and reducing overall circuit overhead.
Solution Approach 2:
The test circuitry employs temporary signal paths and test modes that are activated only when needed for fault detection. During normal operation, these test resources are deactivated or repurposed for functional operations. The system recovers test capabilities when required by switching in test circuits, performing measurements, then discarding the test state and returning to normal operational mode, thereby minimizing permanent complexity overhead.
3Reliability
If comprehensive test coverage is achieved through extensive test circuitry, then reliability improves, but manufacturing cost and device area increase
Solution Approach 1:
The test system implements partial testing strategies where not all possible test paths are simultaneously active. Instead, test circuits selectively activate specific test paths based on the suspected fault location or test objectives. This partial action approach achieves adequate fault coverage for critical paths while avoiding the area overhead of providing complete test coverage for every possible circuit node, optimizing the reliability-to-area ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These techniques improve fault coverage, reliability, and yield of superconductive IC devices by effectively detecting defects and faults within the devices.
Implementation Method 1
Superconductive electronics include superconducting logic circuits (or logic gates) that use superconducting properties for operation. Superconducting logic circuits use a single flux quanta (SFQ), or a magnetic flux quanta, to encode, process, and transport data within the corresponding integrated circuit (IC) device. Such logic circuits are referred to as SFQ circuits. SFQ circuits include Josephson junctions and passive elements such as inductors, resistors, transformers, and/or transmission lines.
Implementation Method 2
Superconductive electronics have zero electrical resistance, and accordingly, the amount of energy used to transmit bits within the corresponding electronic device is minimized, improving the power efficiency of the IC device.
Data Source
AI summary
On-chip testing of a superconductive integrated circuit device includes receiving a superconductive circuit design having superconductive logic elements. Further, a first testability characteristic for first test circuitry at a first node within the superconductive circuit design is determined. The first testability characteristic corresponds to one or more of a test generation control level and a test observability control level. An updated superconductive circuit design from the superconductive circuit design is generated based on the first testability characteristic for the first test circuitry. The superconductive circuit design includes the first test circuitry at the first node.