Interface Circuit Timing Test for Inaccessible 3D-IC Pins
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Solution Overview
Problem
Integrated circuit (IC) devices in directly attached configurations, such as 3D-ICs, pose challenges in testing input and output timing parameters due to inaccessible pins, making it difficult to ensure proper operation and synchronization with clock signals.
Innovation Solution
Incorporating an internal test signal generator and test signal wires that allow for precise adjustment of clock and data signals, enabling the measurement of timing parameters like set-up time, hold time, and clock-to-Q delay, even when ICs are directly bonded and pins are inaccessible to external test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC devices are directly attached in a 3D-IC configuration, then integration density and system performance are improved, but accessibility of pins for testing deteriorates
Solution Approach 1:
The patent introduces an intermediary testing mechanism by embedding test signal generators and test circuits within the IC device itself. These internal test components act as mediators that generate test signals and measure timing parameters without requiring external access to the normally inaccessible pins, thus resolving the contradiction between high integration density and test accessibility.
Solution Approach 2:
The IC device performs self-testing through internally embedded test signal generators and measurement circuits. The device generates its own test signals and measures its own timing parameters (setup time, hold time, clock-to-Q delay) without requiring external test equipment to access the pins, enabling the device to service its own testing needs despite the inaccessible pin configuration.
2Manufacturing precision
If pins are made inaccessible through direct bonding, then manufacturing precision and device reliability are improved, but ability to test timing parameters deteriorates
Solution Approach 1:
The patent embeds intermediary test circuits and signal generators within the IC device that serve as mediators between the inaccessible pins and the testing process. These internal components generate test signals and measure timing parameters without requiring external access, thus preserving both bonding precision and measurement capability.
Solution Approach 2:
The patent transitions the testing approach from external physical access (spatial dimension) to internal signal-based measurement (functional dimension). By embedding test generators and measurement circuits within the device, testing moves from a spatial access problem to a functional signal measurement problem, allowing timing parameters to be measured through internal signal paths rather than external pin access.
3Adaptability or versatility
If internal test circuits are embedded, then test capability is improved, but device complexity increases
Solution Approach 1:
The embedded test signal generators and measurement circuits are designed to test multiple timing parameters (setup time, hold time, clock-to-Q delay) across different interfaces within the IC device. This multi-functional approach allows a single set of internal test components to provide comprehensive testing capability for various timing-critical interfaces, improving test versatility without proportionally increasing complexity.
Data Source
AI summary
A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.