On-Chip Scan Compression Decoding for Scan-Out Bottlenecks
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Solution Overview
Problem
As chips become increasingly complex, existing testing methods require longer times to perform tests, leading to higher costs and production delays, due to the inefficiencies in scan-in and scan-out processes, particularly the slower scan-out process which bottlenecks the testing process.
Innovation Solution
Implementing an on-chip comparator with N input pins to receive scan-in chains, a plurality of scan-chain test registers, and decoding logic to receive a merged expected test-result and masking-instruction signal, allowing for on-chip comparison of test results, thereby reducing the need for external output pins and leveraging the speed advantage of scan-in data input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external testing equipment is used to compare test results with expected results, then testing accuracy is maintained, but test time increases significantly
Solution Approach 1:
The patent merges the comparison function with the test registers by implementing an on-chip comparator that directly compares test results with expected results within the chip itself, eliminating the need to output results externally for comparison. This integration resolves the contradiction by maintaining measurement precision through accurate comparison while dramatically reducing test time by performing comparisons internally during the testing process.
Solution Approach 2:
The patent introduces an intermediary on-chip comparator component that mediates between the test result registers and the external testing equipment. This intermediary performs the comparison function internally, allowing the system to maintain accuracy requirements while avoiding the time-consuming external comparison process.
2Productivity
If multiple scan-in chains are used to increase test throughput, then productivity improves, but the number of pins required increases
Solution Approach 1:
The patent merges multiple expected result signals and their corresponding mask signals into a single merged signal that is received through one pin. This merging allows the system to maintain high productivity with multiple scan-in chains while reducing the pin count required for signal transmission, as multiple data streams are combined into a single communication channel.
Solution Approach 2:
The merged signal serves multiple functions simultaneously, carrying both expected test result information and mask information for multiple scan chains through a single pin. This multi-functionality resolves the contradiction by enabling high throughput operation while minimizing the quantity of pins required.
3Ease of operation
If scan-out process is used to output test results, then testing can be performed, but the process becomes a bottleneck due to slow speed
Solution Approach 1:
Instead of using the slow scan-out process to output test results for comparison, the patent inverts the approach by using the faster scan-in process to input expected results and performing comparisons internally. This inversion resolves the contradiction by maintaining testing capability while dramatically improving speed by eliminating the bottleneck scan-out process.
Solution Approach 2:
The patent replaces the mechanical scan-out process with an electronic comparison mechanism that operates independently of the slow scan-out timing. By substituting the mechanical data movement process with electronic comparison logic, the system maintains ease of operation while achieving much higher speeds.
Data Source
AI summary
A method for testing a chip comprising: receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.