Adder Macrocell Carry Bypass for Wide Crypto Data Paths
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Solution Overview
Problem
Designing arithmetic logic units for crypto processors with large data path widths poses challenges in terms of high design effort, verification, and layout, especially due to the need for calculating units with several hundred bits, which is not efficiently addressed by existing semi-custom and full-custom implementation approaches.
Innovation Solution
A macrocell comprising an adder block with bit-slice adders and a control unit that manages carry signals through a bypass path, allowing dual-rail coded carry signals to be processed efficiently, enabling asynchronous self-clocking and reducing the complexity of timing analysis across multiple macrocells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If arithmetic logic units with large data path widths are designed using classical implementation approaches, then the processing speed and calculation capability are improved, but the design effort, verification complexity, and layout effort increase significantly
Solution Approach 1:
The arithmetic logic unit is divided into multiple macrocells, each processing a portion of the data path. Each macrocell contains segmented functional units (adders, multiplexers, shifters) that can be independently designed and verified, reducing overall design complexity while maintaining large data path width capability
Solution Approach 2:
The macrocell is designed as a universal building block that can perform multiple arithmetic and logic operations through configurable functional units. This multi-functionality allows the same structural template to be reused across different crypto processor designs, reducing design effort for large data path widths
2Productivity
If arithmetic logic units with large data path widths are designed using classical implementation approaches, then the calculation capability for public key cryptography is improved, but the verification effort and design time increase significantly
Solution Approach 1:
Verification is segmented into modular units at the macrocell level. Each macrocell can be independently verified using standardized test benches, and verification results can be composited for the entire large data path unit, significantly reducing total verification effort
Solution Approach 2:
The macrocell design includes built-in feedback mechanisms through carry lookahead logic and validity signals that automatically detect and report verification issues. This automated feedback reduces manual verification effort and accelerates the design verification process
3Productivity
If arithmetic logic units with large data path widths are designed using classical implementation approaches, then the processing performance is improved, but the layout effort and design resources increase significantly
Solution Approach 1:
The layout is segmented into repeating macrocell units that can be automatically instantiated and placed using standard cell design methods. This modular layout approach reduces manual layout effort while achieving large data path widths through systematic replication of proven design blocks
Solution Approach 2:
The macrocell design uses parameterized functional units where data path width and operational characteristics can be configured through parameters rather than redesigning the entire structure. This allows efficient layout adaptation for different crypto processor requirements without proportionally increasing design resources
Data Source
AI summary
A macrocell including an adder block with a plurality of bit-slice adders, a bypass path and a control unit adapted to receive a carry of a first neighboring macrocell, and to output a carry by generation within the adder block or by passage of the carry of the first neighboring macrocell through the bypass path to a second neighboring macrocell. The control unit is adapted to signal a validity of the carry output of the macrocell depending on a logical combination of states of the two carry output lines. The control unit is further adapted, depending on a validity signal of the first neighboring macrocell indicating a validity of the carry, to prevent forwarding the carry.