Computation Using Non-Contact Making Devices TRIZ Cases
- Sub-Binary Analog Computing Calibration for Device Mismatch
Sub-binary radix weights and SRAM multipliers calibrate analog neural computing to curb device mismatch, power use, and output variation.
- Lookup-Table Computing Accelerator for Faster AI Multiplication
Precomputed lookup tables replace floating-point multiplication and dot-product math to cut AI compute time with controlled approximation.
- FPGA DSP Block for Shared AI and Signal Processing Workloads
A reconfigurable FPGA DSP block uses flexible precision and efficient weight loading to handle AI math and signal processing on shared hardware.
- Prime-Number Multiset Encoding for Efficient Security Analytics
Prime-number multiset encoding cuts storage cost while enabling fast add, remove, and identification of user-device connections.
- Partial-Product Truncated Multiplier for Lower Area and Power
Removing least significant bits before partial-product summation cuts multiplier area and power while bias compensation limits truncation error.
- Parallel Neural Inference Elements With Dendritic Tree Architecture
Grouped multipliers, adders, and function blocks enable massively parallel neural inference with lower latency and faster neuron activation processing.
- Floating-to-Fixed Point Conversion Circuit Without Bias Subtraction
Direct exponent-based shifting removes bias subtraction in floating-to-fixed point conversion, cutting circuit hardware and conversion time.
- QR Decomposition Loop Reordering for Parallel FPGA Throughput
Modified Gram-Schmidt loop reordering and ALU-to-ALU FPGA connectivity raise QR decomposition throughput while cutting memory use.
- 3D Lookup-Table Accelerator for Floating-Point Dot Products
Precomputed lookup tables speed floating-point multiplication and vector dot products with 3D memory, symmetry, and zero-skipping.
- In-Memory Vector Multiplication Using Sense Amplifier Logic
Sense circuitry performs AND, OR, and SHIFT operations inside the memory array to cut data transfer, power use, and multiplication time.
- Floating-Point to Fixed-Point Circuit Using Direct Exponent Shifting
Direct exponent-based shifting converts floating-point values to fixed-point format faster while avoiding bias subtraction hardware.
- Reconfigurable DSP Slice for Multi-Mode Arithmetic Processing
A single DSP slice switches across numerical modes with control signals, reducing extra fabric logic and improving processing speed.
- Parallel Neural Inference Elements With Pipelined Partial-Sum Processing
Parallel multipliers, adders, and function blocks overcome sequential neural inference bottlenecks to cut latency and raise throughput.
- Partial-Product Truncation in Multipliers for Lower RF Converter Power
Truncating least significant partial-product bits cuts multiplier area and power, while bias compensation limits quantization noise in RF converters.
- Real Signal Quantization Using Distance-Encoded Nonzero Bits
Distance encoding of selected nonzero bits cuts memory and compute for quantized real signals while preserving precision for multiplication and convolution.
- Fixed-Point Conversion Circuit Using Split-Path Exponent Shifting
A split-path shifter converts floating-point data to fixed-point format without exponent bias subtraction, reducing delay and hardware.
- Floating-Point Intermediate Representation for Order-Independent Summation
An intermediate significand-exponent-shadow format shifts value windows to keep floating-point sums accurate and independent of operand order.
- 3D Configurable Processor with In-Package LUT for Complex Functions
A stacked memory-and-logic processor uses an in-package LUT to handle complex mathematical functions with higher density and a smaller footprint.
- In-Memory Bit-Vector Multiplication Using Embedded Sensing Circuits
Embedded sensing circuitry performs AND, OR, and shift operations inside the memory array, cutting data-transfer time and power.
- Truncated Partial-Product Multiplier With DC Bias Compensation
By removing least significant bits from partial products and compensating DC bias, this multiplier cuts circuit area and power.
- Floating-Point Signal Compression With 4-Bit Exponent Mapping
A 20-bit floating-point format uses 4-bit exponent mapping and 14-bit mantissa allocation to cut signal distortion during I/Q data compression.
- In-Memory Bit-Vector Multiplication Without I/O Data Transfer
Sensing circuitry performs bit-vector multiplication inside the memory array, cutting bus transfer time and power use.
- Floating-Point Bit Remapping for Higher Cache Bus Compression
Rounded LSBs are remapped to MSB positions to expose matching floating-point patterns, improving cache bus compression and cutting transfer power.
- Constant Multiplier Decomposition for Lower-Delay PLD Synthesis
Nearest-boundary decomposition maps constant multipliers into shift and add/subtract logic to cut PLD delay and LUT usage.
- Multifunction Checksum Adder for Area and Power Reduction
A control-bit-driven compression tree and adder combine checksum and fixed-point addition to cut circuit area and power.
- Floating-Point Complex Multiply-Add Circuit With Exponent Alignment
Exponent-aligned mantissa combining lets DSPs execute floating-point complex multiply-add with lower latency, energy use, and logic area.