Pipelined Phase Accumulator to Shorten DDS Carry Chains
Solution Overview
Problem
Conventional phase accumulation in Direct Digital Synthesizers (DDS) and Numerically Controlled Oscillators (NCO) requires lengthy carry chains, which act as a speed-limiting path due to the large number of bits used for fine frequency resolution, leading to significant delays.
Innovation Solution
The implementation of a phase accumulator with parallel pipelined data paths for Most Significant Bits (MSBs) and Least Significant Bits (LSBs), where each bit grouping is processed separately, generating a carry bit for feedback and feed-forward addition, reducing the length of the carry chain and improving speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of bits are used for phase accumulation to achieve fine frequency resolution, then frequency resolution is improved, but the carry chain length increases causing speed degradation
Solution Approach 1:
The phase accumulator is divided into multiple independent adder stages, each handling a portion of the bit width. The carry chain is segmented so that each adder stage processes a subset of bits, reducing the critical path length. This segmentation maintains the full resolution capability while breaking the long carry chain into shorter segments that can be processed in parallel or with reduced delay.
2Measurement precision
If a lengthy carry chain is used to accumulate many bits, then frequency resolution is maintained, but the critical path delay increases limiting operating frequency
Solution Approach 1:
Carry bits are generated and made available in advance for the next addition operation. The carry lookahead logic pre-computes carry signals that can be fed into the next adder stage, reducing the time required for carry propagation. This preliminary generation of carry information allows the adder to complete its operation faster without sacrificing accuracy.
3Speed
If quantization is applied to reduce bit width, then carry chain length is reduced improving speed, but frequency resolution deteriorates
Solution Approach 1:
The system transitions from a single-dimensional approach (single long adder) to a multi-dimensional structure with multiple adder stages processing different bit segments. This dimensional change allows the system to maintain full resolution by combining results from multiple stages, while each individual stage operates faster due to reduced bit width. The parallel or pipelined structure of multiple adders creates a new operational dimension that resolves the speed-precision tradeoff.
Data Source
AI summary
A method for accumulation of information is described. The information is separated into first portions of MSBs and second portions of LSBs. The first and second portions are respectively input to a first adder and a second adder to provide first and second sums. The first and second sums are output from a first and a second storage device for feedback input respectively to the first and second adder to provide the first and second sums. A carry bit output from the second storage device is generated responsive to each wrap condition associated with the storing of the second sums in the second storage device. The carry bit is fed back to the first adder and fed forward for subsequent consolidation with the first sums respectively output from the first storage device. The first sums and the second sums are respectively accumulated as numbers represented in a redundant number system.