Generalized Parallel Counter Structure for FPGA Routing Constraints
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Solution Overview
Problem
In programmable logic devices (PLDs) like FPGAs, ripple-carry adders are inefficient due to routing constraints, while carry-save adders/compressors require excessive logic, making them impractical for implementing multipliers.
Innovation Solution
A modified ternary adder structure is introduced, where logic elements are interconnected to eliminate unused portions, using a logic stage and output stage with selectors and multiplexers to optimize logic usage, allowing for more efficient implementation of generalized parallel counters (GPCs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ripple-carry adders are used in PLDs, then addition operations can be performed, but they do not map well onto available routing structures
Solution Approach 1:
The adder is segmented into multiple full adders that are distributed across different logic elements (LEs) in the PLD. Each LE contains a portion of the adder logic, and the carry signals are routed through the PLD's standard interconnect structure. This segmentation allows the ripple-carry adder to be implemented using the PLD's available routing resources while maintaining functional correctness.
2Ease of manufacture
If carry-save adders/compressors are used, then routing constraints are satisfied, but up to twice the logic of ripple-carry adders is required
Solution Approach 1:
The logic elements are configured to perform multiple functions: they can operate as full adders for ripple-carry addition, as carry-save adders when needed, or as general-purpose logic units. The same physical logic elements and interconnect resources are reused across different operational modes, eliminating the need for separate dedicated logic for each function and reducing overall device complexity.
Data Source
AI summary
Generalized parallel counter circuitry is configured from logic elements—e.g., on a programmable integrated circuit device. Each logic element includes a logic stage, an adder and an output stage. The logic stage includes logic units, and a logic stage selector for selectively outputting to an input of the adder at least one of (a) outputs of the logic units, and (b) a first logic unit output of another one of the logic elements, and for selectively outputting to the output stage one of (a) an output of the logic units, and (b) a first output of the adder. The output stage includes at least two outputs, an output selector for selectively outputting, to the at least two outputs, at least one of (a) a second output of the adder, and (b) an output of the logic stage selector.