Carry-Save Decoder Hardware Reuse for Viterbi and Turbo Instructions
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Solution Overview
Problem
Current implementations of R4ACS Radix-4 Add Compare Select (RACS4) and Radix-4 Add Compare Decision (RACD) instructions for Viterbi decoders and T4MAX/T2MAX Turbo decoders face inefficiencies due to high resource consumption and latency issues, particularly in the propagation of carries during arithmetic operations.
Innovation Solution
The solution optimizes hardware by merging the computation of summation terms using carry-save arithmetic, employing a configurable three-input arithmetic logic unit that performs four arithmetic operations, and leveraging 2's complement arithmetic and selective inversion to facilitate circuit reuse in WiMAX radix-4 turbo decoders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional arithmetic operations are used in Viterbi and Turbo decoders, then decoding functionality is achieved, but latency increases due to carry propagation
Solution Approach 1:
The patent replaces traditional carry-propagation arithmetic operations with carry-save arithmetic operations. Instead of using conventional adders that propagate carries sequentially through multiple logic levels, the invention uses carry-save adders that compute sum and carry bits in parallel without carry propagation, thereby substituting the mechanical carry propagation mechanism with a parallel computation approach that eliminates the latency bottleneck.
Solution Approach 2:
The patent changes the arithmetic operation parameters by transitioning from standard binary addition with carry propagation to carry-save arithmetic. This parameter change involves modifying the fundamental arithmetic operation to compute partial sums and carries simultaneously rather than sequentially, fundamentally altering the computational parameters to achieve reduced latency while maintaining decoding functionality.
2Adaptability or versatility
If separate hardware is implemented for R4ACS/RACD and T2MAX/T4MAX instructions, then both Viterbi and Turbo decoding functions are supported, but hardware resource consumption increases
Solution Approach 1:
The patent implements a universal arithmetic logic unit that can perform multiple arithmetic operations (addition, subtraction, increment, decrement) required by both R4ACS/RACD instructions in Viterbi decoders and T2MAX/T4MAX instructions in Turbo decoders. This single multi-functional unit replaces what would otherwise require separate dedicated hardware for each instruction type, thereby reducing overall hardware resource consumption while maintaining full support for both decoder functionalities.
Solution Approach 2:
The patent merges the computation of summation terms for both Viterbi and Turbo decoding instructions into a single unified arithmetic logic unit. By combining the previously separate hardware resources into one integrated unit that handles both instruction types, the invention reduces hardware duplication and optimizes resource utilization while preserving the adaptability to support both decoding algorithms.
Data Source
AI summary
The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.