Fixed-Point Conversion Circuit Using Split-Path Exponent Shifting
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Solution Overview
Problem
Existing binary logic circuits for converting floating point numbers to fixed point numbers are inefficient due to the need to subtract the exponent bias, which slows down the conversion process and increases hardware requirements.
Innovation Solution
A binary logic circuit that uses a split-path shifter or a single shifter to determine the shift amount from the exponent without subtracting the bias, allowing for efficient conversion by left- or right-shifting the mantissa based on the exponent value, and includes formatting units to align the significand with the fixed point format.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the conventional method of subtracting exponent bias is used to convert floating point to fixed point, then the conversion is accurate, but the conversion time increases and hardware requirements increase
Solution Approach 1:
The patent extracts and eliminates the exponent bias subtraction operation from the conversion process. By using a split-path shifter that directly uses the exponent field value without subtraction, the design removes the harmful subtraction step while maintaining accurate conversion through alternative shift amount determination
Solution Approach 2:
The patent performs preliminary action by pre-determining the shift amount based on the exponent field value and fixed point format requirements before the actual conversion. The split-path shifter is configured to directly use the exponent value to determine shift amounts, eliminating the need for real-time bias subtraction during conversion
2Measurement precision
If the conventional method of subtracting exponent bias is used to convert floating point to fixed point, then the conversion is accurate, but the hardware requirements increase
Solution Approach 1:
The patent extracts and removes the subtraction unit from the hardware architecture. The split-path shifter design directly uses the exponent field value to determine shift amounts, eliminating the need for separate bias subtraction circuitry and reducing overall hardware complexity
Solution Approach 2:
The split-path shifter performs multiple functions: it directly uses the exponent field value to determine shift amounts for both positive and negative exponent cases, and handles both left-shifting and right-shifting operations. This multi-functionality eliminates the need for separate subtraction units and conditional logic circuitry
3Productivity
If a split-path shifter is used to determine shift amount from exponent without subtracting bias, then conversion speed increases, but the shifter complexity increases
Solution Approach 1:
The patent segments the shifter into two independent paths: one for left-shifting (using the exponent value directly) and one for right-shifting (using the complement of the exponent value). This segmentation allows parallel operation of both paths, improving conversion speed while managing complexity through modular design
Solution Approach 2:
The patent implements dynamic path selection based on the exponent value. The first shifter is enabled when left-shifting is required, and the second shifter is enabled when right-shifting is required. This dynamic activation reduces the effective complexity at any given time while maintaining high conversion speed
Data Source
AI summary
A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a first shifter operable to receive a first significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a first output, wherein min{(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number; an inverting unit configured to invert the bit values of the exponent; a second shifter coupled to the inverting unit configured to receive a second significand input comprising a contiguous set of the most significant bits of the significand and configured to right-shift the input by a number of bits equal to the value represented by the p least significant bits of the inverted exponent to generate a second output, wherein min{(ew−1), bitwidth(fw)}≤p≤(ew−1); and a multiplexer coupled to the first and second shifters and configured to: receive a first input comprising a contiguous set of bits of the first output and a second input comprising a contiguous set of bits of the second output; and output the first input if the most significant bit of the exponent is equal to one; and output the second input if the most significant bit of the exponent is equal to zero.