Pre-Adder DSP Circuit for Concurrent Arithmetic Bottlenecks

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Solution Overview

Problem

The increasing demand for real-time, concurrent arithmetic operations in digital signal processing (DSP) applications exceeds the capabilities of traditional DSP chips and Programmable Logic Devices (PLDs), as the latter face bottlenecks due to the limitations of multiple DSP elements programmed in the PLD fabric.

Innovation Solution

A digital signal processing circuit with a pre-adder circuit coupled to a multiplier and multiplexers, and an arithmetic logic unit (ALU) with adder circuits, where the pre-adder circuit can cascade with another pre-adder circuit, enhancing arithmetic operations and improving DSP performance by replacing multiple DSP elements with application-specific circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple DSP elements are configured in the programmable logic and programmable interconnect of the PLD, then concurrent DSP operations are enabled, but the fabric of the PLD becomes a bottleneck

Engineering Contradiction:

Improveconcurrent DSP operationsVSAvoidPLD fabric bottleneck

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the DSP processing function into separate, dedicated components: pre-adder circuits, multiplier circuits, and post-adder circuits. Each component is independently optimized and configured, allowing them to operate in parallel without interfering with each other, thus eliminating the fabric bottleneck while maintaining high concurrent operation capability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces dedicated interconnect structures that act as intermediaries between the pre-adder, multiplier, and post-adder circuits. These specialized interconnect paths bypass the general-purpose PLD fabric, providing high-speed data transfer channels that eliminate the fabric bottleneck while enabling efficient concurrent operations

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If traditional DSP chips are used, then programmable processing is achieved, but the increasing demand for real-time arithmetic operations exceeds their capabilities

Engineering Contradiction:

Improveprogrammable processingVSAvoidreal-time arithmetic operations

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent creates a universal DSP circuit configuration that can perform multiple arithmetic operations (addition, subtraction, multiplication, accumulation) through a standardized set of pre-adder, multiplier, and post-adder circuits. This multi-functional design maintains programmability while achieving the high-speed real-time processing required by modern DSP applications

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements pre-adder circuits that perform addition operations before the multiplication stage, and post-adder circuits that perform addition after multiplication. This preliminary and follow-up action structure enables efficient implementa

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7844653B2Digital signal processing circuit having a pre-adder circuit

Publication Date: 2010.11.30 XILINX INC

AI summary

A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.