Floating-to-Fixed Point Conversion Circuit Without Bias Subtraction
Solution Overview
Problem
Existing binary logic circuits for converting floating point numbers to fixed point numbers are inefficient due to the need to subtract the exponent bias, which slows down the conversion process and increases hardware requirements.
Innovation Solution
A binary logic circuit that uses a split-path shifter or a single shifter to determine the shift for the mantissa based on the exponent, eliminating the need for exponent bias subtraction by exploiting the knowledge of the exponent values, and includes formatting units to align the significand with the fixed point format.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exponent bias subtraction is performed in the conversion circuit, then the floating point to fixed point conversion can be completed with standard algorithm, but the conversion time increases and hardware requirements increase
Solution Approach 1:
The patent extracts and eliminates the exponent bias subtraction operation from the conversion circuit. By recognizing that the exponent field already contains the biased value and directly using it for the shift operation without subtracting the bias, the circuit removes an unnecessary computational step. This extraction of the bias subtraction operation resolves the contradiction by maintaining conversion accuracy while reducing conversion time.
Solution Approach 2:
The patent changes the parameter interpretation approach: instead of treating the exponent as a biased value that requires subtraction to get the true exponent, the circuit directly uses the biased exponent value as the shift amount. This parameter change eliminates the need for bias subtraction while still achieving correct fixed point conversion, thereby reducing conversion time without sacrificing accuracy.
2Reliability
If exponent bias subtraction is performed in the conversion circuit, then the conversion can be completed using standard floating point interpretation, but the hardware requirements and circuit complexity increase
Solution Approach 1:
The patent extracts and removes the exponent bias subtraction unit from the conversion circuit. By directly using the exponent field value as the shift amount without performing subtraction, the circuit eliminates the need for additional subtractor hardware. This extraction resolves the contradiction by maintaining conversion accuracy while reducing circuit complexity and hardware requirements.
3Device complexity
If a single shifter is used instead of split-path shifter, then the hardware requirements are reduced, but the conversion process becomes more complex
Solution Approach 1:
The patent designs a single shifter that can perform both left-shift and right-shift operations based on the exponent value. This universal shifter replaces the need for separate left-shifter and right-shifter circuits (split-path architecture). The single shifter is controlled by the exponent field to determine the appropriate shift direction and amount, achieving the same conversion functionality with reduced hardware requirements while maintaining conversion speed through efficient single-unit operation.
Data Source
AI summary
A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min {(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.