Pipelined FFT Butterfly Architecture for Flexible 3×2N Transforms

The patent combines Radix-2 and Radix-4 butterfly structures into a unified hardware architecture. The Radix-4 butterfly circuit processes four input samples simultaneously, while Radix-2 stages handle pairs of samples. This merging allows the same hardware to efficiently compute FFTs of sizes that are powers of 2 (via Radix-2 stages) and sizes that are 4 times a power of 2 (via Radix-4 stages), thereby resolving the contradiction between implementation simplicity and size flexibility.

The patent implements dynamic reconfiguration capability where the hardware can switch between operating as Radix-2 stages or Radix-4 stages based on the required FFT size. Control logic dynamically adjusts the butterfly circuit operation mode, enabling the system to adapt its processing structure to match the input data size requirements, thus achieving both simplicity and versatility.

The patent transitions from sequential multi-pass processing to parallel simultaneous processing by introducing a second spatial dimension for computation. Multiple butterfly stages operate concurrently on different data segments within the same clock cycle, effectively transforming the time dimension into a parallel processing architecture. This allows 2D FFT computation to be performed in a single pass through the hardware, maintaining processing completeness while dramatically reducing computation time.

The patent ensures continuous useful action by keeping all butterfly circuits actively processing data simultaneously without idle cycles between passes. The pipelined architecture maintains a steady flow of data through multiple stages, eliminating the gaps and waiting periods inherent in sequential multi-pass approaches, thereby achieving both complete processing and reduced computation time.