Floating-Point Adder Circuit with Same-Sign Sum and Difference Paths
Solution Overview
Problem
In tightly constrained devices like mobile devices, there is a trade-off between power consumption, processing performance, and silicon area when implementing floating-point addition in hardware, and existing solutions do not efficiently address this balance.
Innovation Solution
The method involves identifying floating-point numbers with the same sign and using same-sign adders to process them, reducing the need for mixed-sign adders, and arranging these adders in a tree structure with multiplexing logic to efficiently add multiple numbers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If same-sign floating-point adders are used to add at least three floating-point numbers, then processing performance and power consumption are improved, but device complexity increases due to the need for sign identification and separate adder circuits
Solution Approach 1:
The adder circuit is segmented into multiple same-sign floating-point adders, each dedicated to adding numbers with specific sign combinations. This segmentation allows each adder to be optimized for its specific function, improving processing performance while managing complexity through modular design. The circuit identifies sign combinations and routes numbers to appropriate adders, maintaining high efficiency without requiring a single complex mixed-sign adder.
2Adaptability or versatility
If mixed-sign floating-point adders are used to add floating-point numbers with different signs, then adaptability is improved, but silicon area and power consumption increase
Solution Approach 1:
Instead of using a single mixed-sign adder that handles all sign combinations, the circuit segments the addition function into multiple same-sign adders. Each adder handles a specific sign combination (e.g., positive-positive, negative-negative), which reduces the complexity and silicon area of each individual adder while maintaining overall adaptability through the multiplexer network that selects the appropriate adder based on input signs.
Solution Approach 2:
The multiplexer network provides universality by routing different input combinations to the appropriate same-sign adders. This multi-functional approach allows the circuit to handle mixed-sign additions without requiring a complex mixed-sign adder, as the same-sign adders are universally applied through selective routing based on the signs of the input numbers.
3Use of energy by stationary object
If hardware implementation is used for floating-point addition, then power consumption and latency are reduced, but flexibility is lost compared to software implementation
Solution Approach 1:
The hardware circuit incorporates dynamic elements through the multiplexer network that adapts its routing based on the signs of the input numbers. This dynamic configuration allows the fixed-function same-sign adders to handle various addition scenarios (same-sign and mixed-sign) without requiring reconfiguration of the adder circuits themselves, maintaining hardware efficiency while providing operational flexibility.
Data Source
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AI summary
Circuits and associated methods are disclosed, for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A-B) of the two numbers. The method comprises calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|-|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A-B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|-|B|), and the sign of each floating-point number.