Hardware Data Compression Circuit for Memory Bandwidth Limits
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Solution Overview
Problem
Existing data compression methods for matrix structures incur significant computation costs and processing speed limitations due to their complexity, particularly when decompressing data in processors, which results in large and slow apparatuses with high memory access costs.
Innovation Solution
A hardware-based compression and decompression circuit that stores data in a compressed format using a map to identify non-zero values, allowing for efficient retrieval and reconstruction of the original data structure, reducing memory bandwidth requirements and processing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If software-based compression methods (such as bitmap table, signMap table, and dataMap table) are used to compress matrix structures, then memory storage requirements are reduced, but the computation cost and processing speed deteriorate significantly due to complexity in both compression and decompression
Solution Approach 1:
The patent replaces software-based compression/decompression algorithms with dedicated hardware circuits. The compression circuit uses comparators to identify non-zero elements and generates compressed representations in hardware, while the decompression circuit reconstructs original data structures through hardware-based operations. This mechanical/electrical substitution eliminates the computational overhead of software processing, achieving both compression and rapid decompression in parallel hardware operations.
2Quantity of substance
If complex compression algorithms are implemented in processors, then data compression ratio is improved, but the apparatus size and implementation cost increase
Solution Approach 1:
The patent divides the compression and decompression functions into separate dedicated hardware circuits. The compression circuit is segmented into comparators for identifying non-zero elements and logic for generating compressed representations. The decompression circuit is segmented into dedicated hardware for reconstructing data structures. This segmentation allows each component to be optimized independently, achieving effective compression without requiring a monolithic complex processor implementation.
3Productivity
If memory bandwidth is increased to overcome the memory-wall limitation, then computation performance is improved, but the cost and complexity of the memory system increases
Solution Approach 1:
The patent extracts the compression function from the main memory system and implements it in dedicated hardware circuits. By compressing data before storage and decompressing upon retrieval, the system reduces the volume of data that must be transferred through the memory subsystem. This extraction of the compression function from the memory path allows the memory system to operate at lower bandwidth requirements while maintaining computation performance, avoiding the need for complex high-bandwidth memory solutions.
Data Source
AI summary
The present application addresses a fundamental problem in the design of computing systems, that of minimizing the cost of memory access. This is a fundamental limitation on the design of computer systems as regardless of the memory technology or manner of connection to the processor, there is a maximum limitation on how much data can be transferred between processor and memory in a given time, this is the available memory bandwidth and the limitation of compute power by available memory bandwidth is often referred to as the memory-wall. The solution provided creates a map of a data structure to be compressed, the map representing the locations of non-trivial data values in the structure (e.g. non-zero values) and deleting the trivial data values from the structure to provide a compressed structure.