Configurable IC Carry Chain Layout With Direct Tile Interconnects
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Solution Overview
Problem
Existing configurable IC architectures are inefficient due to redundant connections and high costs associated with transistor switching logic, particularly in connecting non-diagonally adjacent tiles, leading to suboptimal interconnectivity and reachability between computational tiles.
Innovation Solution
The development of a configurable IC architecture with direct offset connections between computational tiles, allowing for increased interconnectivity by using wire segments across multiple wiring layers and vias, along with buffer circuits to maintain signal integrity and reduce noise, thereby reducing the need for redundant connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistor switching logic is used to connect non-diagonally adjacent tiles, then interconnectivity between tiles is achieved, but device complexity and cost increase significantly
Solution Approach 1:
The patent extracts the switching logic from the interconnect structure by using direct wire segments instead of transistor-based switches. The interconnect circuit is simplified to use passive wire segments that directly connect computational tiles without requiring active switching elements, thereby reducing device complexity while maintaining interconnectivity.
Solution Approach 2:
The patent uses replicated wire segment patterns across multiple wiring layers to create redundant connection paths. Instead of using complex switching logic to route signals, the design copies simple wire segment structures across layers to provide multiple direct connection options between tiles, reducing the need for sophisticated interconnect control.
2Adaptability or versatility
If transistor switching logic is used for interconnect circuits, then routing functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive transistor switching elements with inexpensive wire segments for interconnect routing. The wire segments serve as simple, low-cost conductive paths that can be manufactured using standard wiring layer processes, significantly reducing manufacturing cost compared to transistor-based switching logic while maintaining routing functionality.
3Adaptability or versatility
If direct wire segments across multiple wiring layers are used, then interconnectivity between non-adjacent tiles is improved, but signal integrity may deteriorate due to noise
Solution Approach 1:
The patent introduces buffer circuits as intermediary elements between the wire segments and computational tiles. These buffers act as signal regeneration stations that receive signals from long wire segments across multiple layers, amplify and clean them, and retransmit them to the destination tile, thereby maintaining signal integrity despite the extended connection paths.
4Device complexity
If redundant connections are eliminated, then device complexity and cost are reduced, but reachability between tiles may be compromised
Solution Approach 1:
The patent transitions from planar two-dimensional interconnect routing to three-dimensional routing by utilizing multiple wiring layers stacked vertically. This dimensional change allows direct connections between non-adjacent tiles through vertical vias and wire segments across layers, providing reachability without requiring redundant horizontal connections, thus reducing device complexity while maintaining connectivity.
Data Source
AI summary
Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.