Floating-Point Bit Remapping for Higher Cache Bus Compression
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Solution Overview
Problem
Existing compression algorithms for floating-point numbers are not adaptive to rounded bits, leading to reduced compressibility and increased power consumption in cache and memory operations.
Innovation Solution
A method that rounds bits in the least significant positions of floating-point numbers to a uniform binary value and maps them to the most significant positions, using techniques like shift or hashing functions, to expose more matching patterns for efficient compression using algorithms like MPack or Frequent-Pattern Compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If lossy compression techniques round the least significant bits of floating point numbers to zeros, then the compressibility of floating point numbers is improved, but the compression algorithm must be modified to be aware of rounded bits which impacts overall compressibility
Solution Approach 1:
The patent applies preliminary action by performing bit remapping before compression to expose matching patterns. The least significant bits are rounded to zeros, then a remapping operation shifts these rounded bits to more significant positions, creating predictable patterns that the compression algorithm can exploit before the actual compression occurs.
Solution Approach 2:
The patent changes the parameter arrangement of bits through remapping. By transforming the position of rounded bits from least significant to more significant positions, the patent alters the bit pattern structure to enhance compressibility without changing the fundamental compression algorithm.
2Loss of energy
If data compression is implemented to reduce on-chip and off-chip bandwidth usage, then power dissipation is reduced, but compression and decompression operations require additional hardware power overhead
Solution Approach 1:
The patent applies partial action by implementing selective bit remapping only on the least significant bits that are rounded to zeros, rather than processing all bits. This partial transformation reduces the computational overhead of the remapping operation while still achieving the primary goal of enhancing compressibility for the significant bit patterns.
3Loss of substance
If floating point numbers are compressed without bit remapping, then the compression algorithm operates simpler, but matching patterns between floating point numbers are not exposed reducing compressibility
Solution Approach 1:
The patent applies preliminary action by performing bit remapping before compression to expose matching patterns. The least significant bits are rounded to zeros, then a remapping operation shifts these rounded bits to more significant positions, creating predictable patterns that the compression algorithm can exploit before the actual compression occurs.
Data Source
AI summary
Methods and systems of reducing power transmitted over a memory to cache bus having a plurality of cache lines by identifying floating point numbers transmitted over a cache line, rounding bits in least significant bit (LSB) positions of identified floating point (FP) numbers to a uniform binary value string, mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each FP number to increase a chance of matching bit patterns between pairs of the FP numbers, and compressing the floating point numbers by replacing matched bit patterns with smaller data elements using a defined data compression process. A decompressor decompresses the compressed FP numbers using a defined decompression process corresponding to the defined compression process; and the mapping component applies a reverse mapping function to map the rounded bits back to original LSB positions from the MSB positions to recover the original floating point numbers.