Bit-Slice Register Bus Architecture to Reduce Cross Currents
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Solution Overview
Problem
Existing calculating units with fewer bit slices than operand positions face inefficiencies due to complex control and high cross currents when processing large operands, leading to increased chip complexity and cost.
Innovation Solution
Connecting register cells in parallel within each bit slice, allowing selective control and minimizing cross currents by ensuring only one cell is coupled to the communication bus at a time, with dual rail implementation for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If register cells are connected in series within each bit slice, then data can be transmitted through the communication bus, but control complexity increases and cross currents increase
Solution Approach 1:
The patent inverts the conventional series connection approach by implementing parallel connection of register cells to the communication bus. Each register cell has its own direct connection to the bus, and a selector mechanism chooses which cell is actively coupled. This inversion from series to parallel architecture fundamentally simplifies control logic while maintaining data transmission capability.
Solution Approach 2:
The patent segments the communication interface by providing separate, independent connections from each register cell to the communication bus. Instead of a single shared path (series), each cell has its own dedicated path, allowing independent control and reducing the complexity of coordination between cells.
2Productivity
If multiple register cells are coupled to the communication bus simultaneously, then data transfer efficiency increases, but cross currents increase leading to higher power consumption
Solution Approach 1:
The patent implements a dynamic coupling mechanism where the connection between register cells and the communication bus is not static but controllable. A selector circuit dynamically couples only the currently active register cell to the bus while decoupling others, optimizing power consumption by minimizing simultaneous active connections while maintaining efficient data transfer when needed.
3Area of stationary object
If the calculating unit has fewer bit slices than operand positions, then chip area is reduced, but processing capability is limited
Solution Approach 1:
The patent makes each bit slice universal by equipping it with multiple register cells (typically 2-4 cells per slice) that can handle multiple operand positions. This multi-functionality allows a reduced number of bit slices to process operands with more positions, as each slice can sequentially or selectively access different register cells to accommodate various operand lengths and operations.
Solution Approach 2:
The patent implements a nested structure where multiple register cells are contained within each bit slice. This nesting allows the register cells to be organized hierarchically, with the selector mechanism enabling access to nested cells in a controlled manner, effectively packing more storage capacity into fewer slices while maintaining processing efficiency.
Data Source
AI summary
A calculating unit including a number of bit slices which is less than the number of positions of the operand to be processed. Each bit slice has a logic element and a communication bus between the logic element and the plurality of register cells. The register cells are connected in parallel with respect to the slice-internal communication bus and are controlled by a controller so that only one register cell of the plurality of register cells is coupled to the communication bus at a time.