Partial-Product Truncated Multiplier for Lower Area and Power
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Solution Overview
Problem
Conventional digital down converters (DDCs) and up converters (DUCs) face challenges due to complex and power-consuming digital circuitry required for high-speed RF sampling, leading to increased circuit area and power consumption as performance demands rise.
Innovation Solution
The implementation of a multiplier architecture that truncates partial products before summation, reducing circuit complexity and area, accompanied by bias compensation to mitigate quantization noise and DC bias introduced by truncation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital down converters use full-precision multiplication circuitry, then multiplication accuracy is maintained, but circuit area and power consumption increase significantly
Solution Approach 1:
The patent extracts and removes the least significant bits from partial products during the multiplication process. By discarding these less critical bits, the circuit achieves significant area reduction while maintaining sufficient accuracy for the application, directly resolving the contradiction between precision and area.
Solution Approach 2:
The patent applies partial action by performing multiplication with reduced precision rather than full precision. The truncation of partial products represents a deliberate choice to use slightly less precision (removing LSBs) to achieve the primary goal of area reduction, which is acceptable for the intended application.
2Measurement precision
If conventional digital down converters use full-precision multiplication circuitry, then multiplication accuracy is maintained, but power consumption increases
Solution Approach 1:
By extracting and removing the least significant bits from partial products, the patent reduces the number of computational operations and the complexity of the summation circuitry. This directly reduces power consumption while maintaining sufficient multiplication accuracy for the application.
Solution Approach 2:
The patent uses partial action by performing multiplication with truncated precision rather than full precision. This reduces the computational burden and power consumption of the multiplier circuit while maintaining adequate accuracy for digital down conversion applications.
3Area of stationary object
If partial products are truncated by removing least significant bits, then circuit area is reduced, but quantization noise and DC bias are introduced
Solution Approach 1:
The patent converts the harmful effect of truncation (quantization noise and DC bias) into a manageable issue by designing the system to tolerate or compensate for these effects. The truncation itself is the beneficial action that reduces area, and the resulting noise and bias are accepted as trade-offs that do not significantly degrade overall system performance.
Data Source
AI summary
A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.