Multifunction Checksum Adder for Area and Power Reduction

Solution Overview

Problem

Existing hardware circuits for checksum operations are inefficient in terms of area and power consumption, and lack the ability to seamlessly integrate checksum and fixed point addition functions.

Innovation Solution

A hardware circuit incorporating a multifunction compression tree and adder that can switch between fixed point and checksum addition schemes based on a control bit, allowing for efficient execution of both operations on the same hardware element.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate hardware circuits are used for checksum operations and fixed point addition, then functional versatility is improved, but area and power consumption increase

Engineering Contradiction:

Improvefunctional versatilityVSAvoidarea

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements a multifunctional hardware circuit that can operate in two distinct modes: checksum addition mode and fixed-point addition mode. The same physical circuitry performs both functions by responding to different control signals, eliminating the need for separate dedicated circuits for each operation type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The circuit employs dynamic control mechanisms where control signals adjust the operational behavior of the adder based on the desired function. The control logic dynamically reconfigures the circuit's operation between checksum and fixed-point addition modes, allowing adaptability without physical reconfiguration.

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If separate hardware circuits are used for checksum operations and fixed point addition, then functional versatility is improved, but power consumption increases

Engineering Contradiction:

Improvefunctional versatilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent implements a multifunctional hardware circuit that can operate in two distinct modes: checksum addition mode and fixed-point addition mode. The same physical circuitry performs both functions by responding to different control signals, eliminating the need for separate dedicated circuits for each operation type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the checksum addition function and fixed-point addition function into a single integrated hardware circuit. By combining these previously separate functions into one unified circuit, the patent reduces overall power consumption while maintaining full functional capability for both operation types.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If dedicated checksum hardware is implemented, then checksum operation performance is improved, but device complexity increases

Engineering Contradiction:

Improvechecksum operation performanceVSAvoiddevice complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a multifunctional hardware circuit that can operate in two distinct modes: checksum addition mode and fixed-point addition mode. The same physical circuitry performs both functions by responding to different control signals, eliminating the need for separate dedicated circuits for each operation type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9436434B2Checksum adder

Publication Date: 2016.09.06 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.