Photonic Clock Distribution for Low-Power ML Processor Fabrics
Solution Overview
Problem
Existing AI computing systems, particularly those implementing machine learning models, face challenges with high power consumption and inefficiency in data movement due to reliance on electrical interconnects and SerDes blocks, which are power-inefficient for MAC operations and result in significant energy expenditure.
Innovation Solution
Implementing a hybrid electro-photonic network-on-chip (NoC) within circuit packages, utilizing bidirectional photonic channels for intra-chip and inter-chip data movement, combined with a novel clocking scheme and power-efficient MAC operations, to reduce power consumption and increase processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If electrical interconnects and SerDes blocks are used for data transfer between chips, then data communication is achieved, but power consumption increases significantly
Solution Approach 1:
The patent replaces electrical signal transmission with optical signal transmission using photonic channels. Light signals are used to carry data between processing elements and between chips, eliminating the need for electrical interconnects and SerDes blocks. This substitution of electrical domain with optical domain significantly reduces power consumption while maintaining high data transfer efficiency.
Solution Approach 2:
The patent changes the fundamental parameter of signal transmission from electrical to optical. By using photonic channels with different physical characteristics (light propagation instead of electrical current), the system achieves lower power consumption and higher bandwidth. The optical signals can carry more data with less energy expenditure compared to traditional electrical interconnects.
2Productivity
If data is moved over chip-level interconnects to SerDes for transmission, then off-chip communication is enabled, but energy expenditure increases
Solution Approach 1:
The patent substitutes electrical data movement with optical data movement throughout the system. Processing elements communicate directly via photonic channels both within and between chips, eliminating the energy-intensive process of moving data over electrical interconnects to SerDes blocks for conversion and transmission. This direct optical communication path maintains high data transfer speed while dramatically reducing energy expenditure.
3Speed
If traditional clock distribution networks are used, then clock signals are delivered to processing elements, but power is wasted and skew accumulates
Solution Approach 1:
The patent replaces traditional electrical clock distribution networks with optical clock signal transmission. Clock signals are delivered through photonic channels directly to processing elements, eliminating the power-wasting and skew-prone electrical interconnects. The optical clock distribution maintains synchronized timing across all processing elements while consuming less power and avoiding signal degradation.
4Adaptability or versatility
If SerDes blocks are used for data conversion, then parallel-to-serial conversion is achieved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent eliminates SerDes blocks by using optical communication that can directly handle data transmission without requiring parallel-to-serial conversion hardware. The photonic channels enable direct data transfer between processing elements and memory devices, removing the need for complex SerDes blocks that convert between parallel and serial formats. This simplification reduces hardware complexity and power consumption while maintaining data format adaptability.
Data Source
AI summary
Various embodiments provide for clock signal distribution within a processor, such as a machine learning (ML) processor, using a photonic fabric.