Floating-Point Complex Multiply-Add Circuit With Exponent Alignment
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Solution Overview
Problem
Existing digital signal processors and hardware accelerators face challenges in efficiently performing floating-point complex multiply-add operations, which are critical for signal processing, due to the complexity and silicon area requirements of separate real and imaginary component calculations.
Innovation Solution
A method and apparatus that align and combine the mantissas of complex numbers with the largest exponent, allowing for a single process to perform both multiplication and addition, using carry-save adders and two-input full adders to reduce latency and energy consumption, while avoiding normalization and truncating unnecessary precision bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate real and imaginary component calculations are performed for floating-point complex multiply-add operations, then calculation accuracy is maintained, but processing time increases and silicon area requirements increase
Solution Approach 1:
The patent combines separate real and imaginary component calculations into a unified floating-point complex multiply-add operation. The method aligns exponents of input operands, performs mantissa multiplication and addition in a unified process, and generates both real and imaginary results simultaneously through shared computational paths, thereby reducing processing time while maintaining accuracy.
Solution Approach 2:
The invention creates a multi-functional computational unit that handles both multiplication and addition operations for complex numbers in a single process. The unified algorithm processes real and imaginary components through common exponent alignment and mantissa processing stages, allowing the same hardware structure to perform multiple mathematical operations efficiently.
2Measurement precision
If separate real and imaginary component calculations are performed, then complete mathematical precision is achieved, but silicon area increases
Solution Approach 1:
The patent merges separate calculation paths for real and imaginary components into a unified computational structure. By sharing exponent alignment logic, mantissa multiplication units, and addition circuits between real and imaginary computations, the design reduces the total silicon area required while preserving complete mathematical precision through proper handling of all computational stages.
3Measurement precision
If floating-point calculations are performed with full precision, then accuracy is maintained, but energy consumption increases
Solution Approach 1:
The patent performs preliminary exponent alignment before mantissa multiplication, determining the maximum exponent in advance and pre-shifting all operands to a common exponent baseline. This preliminary normalization reduces the complexity of subsequent multiplication and addition operations, lowering energy consumption while maintaining full floating-point accuracy throughout the calculation process.
4Ease of operation
If complex multiplication and addition are performed as separate operations, then operational clarity is maintained, but processing latency increases
Solution Approach 1:
The invention merges complex multiplication and addition into a single unified operation called complex multiply-add (CMAD). The unified process computes real and imaginary results simultaneously through integrated computational paths, eliminating the sequential execution overhead between separate multiplication and addition operations, thereby reducing processing latency while maintaining operational clarity through a well-defined unified algorithm.
Data Source
AI summary
An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.