Sub-Binary Analog Computing Calibration for Device Mismatch
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Solution Overview
Problem
Analog computing systems face challenges due to device mismatch in transistors, leading to output variation and increased power consumption and chip area requirements in digital circuits used in neural networks, which affects the accuracy and efficiency of machine learning processes.
Innovation Solution
The implementation of a sub-binary radix weight representation to calibrate analog circuits, reducing output variation and power consumption by using SRAM-based Sub-Binary Multipliers (SSBM) that perform multiplication and addition operations with less chip area and power, and incorporating a calibration module to mitigate device mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital circuits are used to implement multiplication and addition processes in neural networks, then computing accuracy is maintained, but power consumption increases and chip area expands
Solution Approach 1:
The patent replaces digital circuit multiplication and addition operations with analog circuit operations. Specifically, analog multipliers perform multiplication by generating output currents proportional to the product of input voltages and stored weight values, while analog adders sum these currents directly. This substitution of digital mechanical/logical operations with analog physical operations reduces power consumption and chip area while maintaining computing accuracy through calibrated weight representation.
2Use of energy by stationary object
If analog circuits are used to perform multiplication and addition operations, then power consumption and chip area are reduced, but device mismatch causes output variation
Solution Approach 1:
The patent changes the parameter representation from binary to sub-binary radix. Weight values are represented using sub-binary radix digits (0, 1, 2) instead of binary digits (0, 1). This parameter change allows for calibrated weight representation that compensates for device mismatch. The calibration process adjusts the sub-binary radix weight values to account for variations in analog device characteristics, thereby maintaining output accuracy while benefiting from reduced power consumption and chip area.
3Area of stationary object
If device dimensions are reduced to increase integration density, then chip area decreases, but device mismatch increases causing more output variation
Solution Approach 1:
The patent employs sub-binary radix weight representation with calibration to compensate for increased device mismatch resulting from smaller device dimensions. The calibration module adjusts the weight parameters in sub-binary radix format to account for variations introduced by scaled-down device geometry. This allows the system to achieve high integration density with reduced chip area while maintaining output accuracy through parameter calibration.
4Area of stationary object
If digital circuits are reused with different input signals and memory storage, then chip area is reduced, but data transferring increases slowing down processing
Solution Approach 1:
The patent implements continuous analog computing operations where input signals are continuously processed through analog multipliers and adders. Unlike digital systems that require discrete read-write cycles and data transfer to memory, the analog circuit maintains continuous operation with direct signal flow from inputs through computation to outputs. This continuity eliminates data transferring bottlenecks and enables real-time processing, significantly improving productivity while using less chip area.
Data Source
AI summary
A system for analog computing, an analog computing system with sub-binary radix weight representation is provided. The analog computing system comprises an input node, a multiplexer (MUX), a digital to analog converter (DAC), a SRAM-based Sub-Binary Multiplier (SSBM), an analog to digital converter (ADC), a switch, an output node and a calibration module. The calibration module is configured to control the analog computing system to switch between a calibration mode and a normal operation mode. Prior to being switched to the normal operation mode, the analog computing system is configured to perform a process to calibrate a weight parameter stored in the SSBM. The ADC comprises a plurality of multipliers associated with a plurality of sub-binary weight radixes. The weight parameter stored in the SSBM and the plurality of sub-binary weight radixes are configured to represent a plurality of weights for the analog computing system.