Floating-Point to Fixed-Point Circuit Using Direct Exponent Shifting
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Solution Overview
Problem
Converting floating point numbers to fixed point numbers in binary logic circuits is inefficient due to the need to subtract the exponent bias, which slows down the conversion process and increases hardware requirements.
Innovation Solution
A binary logic circuit with split-path shifters or single shifters that determine the shift amount directly from the exponent, eliminating the need for exponent bias subtraction by using offset units and formatting units to align the significand with the fixed point format, allowing for efficient conversion of floating point numbers to fixed point numbers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If exponent bias subtraction is used to convert floating point to fixed point, then conversion accuracy is maintained, but conversion speed decreases and hardware complexity increases
Solution Approach 1:
The patent extracts and eliminates the exponent bias subtraction operation from the conversion process. By using a split-path shifter design where one path handles the exponent directly without subtraction, the circuit removes the harmful subtraction step while maintaining conversion accuracy through alternative alignment mechanisms.
Solution Approach 2:
The patent segments the shifter into multiple paths: a fast path that uses the exponent directly and a slow path that performs bias subtraction. This segmentation allows the circuit to achieve high-speed conversion for most cases while maintaining accuracy for edge cases, resolving the contradiction between speed and precision.
2Measurement precision
If exponent bias subtraction is used to convert floating point to fixed point, then conversion accuracy is maintained, but hardware complexity increases
Solution Approach 1:
The patent removes the subtraction unit from the critical conversion path by extracting the bias value and using it to pre-calculate shift amounts in lookup tables. This eliminates the need for real-time exponent subtraction hardware, reducing circuit complexity while preserving conversion accuracy.
Solution Approach 2:
The patent performs preliminary action by pre-calculating bias-adjusted shift amounts and storing them in lookup tables. This eliminates the need for real-time subtraction operations during conversion, reducing hardware complexity while maintaining accuracy through pre-computed values.
3Measurement precision
If traditional conversion circuitry is used, then accurate conversion is achieved, but conversion time increases
Solution Approach 1:
The patent implements a dynamic conversion circuit that adapts its operation based on the exponent value. The split-path shifter dynamically selects between fast and slow conversion paths, optimizing conversion time while maintaining accuracy across different input ranges.
Solution Approach 2:
The patent uses preliminary action by pre-computing shift amounts and storing them in lookup tables based on exponent values. This eliminates real-time subtraction operations, significantly reducing conversion time while maintaining accuracy through pre-calculated values.
Data Source
AI summary
A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.