Partial-Product Truncation in Multipliers for Lower RF Converter Power
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Solution Overview
Problem
Conventional digital down converters (DDCs) and digital up converters (DUCs) face increased complexity and power consumption due to high-speed radio frequency (RF) sampling, leading to large circuitry area and power consumption, especially as performance requirements rise.
Innovation Solution
A multiplier architecture that truncates partial products before summation, reducing circuit complexity and area, and incorporates bias compensation to mitigate quantization noise, specifically including a partial product generation circuit, truncation circuit, and summation circuit with a bias compensation mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional digital down converters and digital up converters are used with high-speed RF sampling, then performance requirements are met, but circuit complexity and power consumption increase significantly
Solution Approach 1:
The patent extracts and removes the least significant bits from partial products during the multiplication process. By taking out these less critical bits through truncation circuits, the overall circuit complexity is reduced while maintaining the essential functionality of the multiplier, thus resolving the contradiction between performance and circuit complexity.
Solution Approach 2:
The patent applies partial action by not computing all bits of the partial products fully. Instead, it computes only the necessary most significant bits and truncates the remaining less significant bits. This partial computation approach reduces circuit complexity while maintaining sufficient performance for the application.
2Reliability
If conventional digital down converters and digital up converters are used with high-speed RF sampling, then performance requirements are met, but power consumption increases significantly
Solution Approach 1:
The patent extracts and removes the least significant bits from partial products during the multiplication process. By taking out these less critical bits through truncation circuits, the overall circuit complexity is reduced while maintaining the essential functionality of the multiplier, thus resolving the contradiction between performance and circuit complexity.
Solution Approach 2:
The patent applies partial action by not computing all bits of the partial products fully. Instead, it computes only the necessary most significant bits and truncates the remaining less significant bits. This partial computation approach reduces circuit complexity while maintaining sufficient performance for the application.
3Device complexity
If partial products are truncated to reduce circuit area, then circuit complexity and area are reduced, but quantization noise and bias are introduced
Solution Approach 1:
The patent converts the harmful effect of truncation (quantization noise and bias) into a manageable issue by introducing compensation circuits. These circuits calculate and add compensation values that counteract the bias introduced by truncation, thereby converting the harmful information loss into a corrected result that maintains accuracy while benefiting from reduced circuit area.
4Speed
If high-speed RF sampling is implemented, then next-generation wireless receiver performance is achieved, but ADC and digital processing requirements increase
Solution Approach 1:
The patent extracts and removes the least significant bits from partial products during the multiplication process. By taking out these less critical bits through truncation circuits, the overall circuit complexity is reduced while maintaining the essential functionality of the multiplier, thus resolving the contradiction between performance and circuit complexity.
Solution Approach 2:
The patent applies partial action by not computing all bits of the partial products fully. Instead, it computes only the necessary most significant bits and truncates the remaining less significant bits. This partial computation approach reduces circuit complexity while maintaining sufficient performance for the application.
Data Source
AI summary
A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.