In-Memory Bit-Vector Multiplication Without I/O Data Transfer
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Solution Overview
Problem
Existing memory devices require significant power and time to perform multiplication operations, as they often necessitate transferring data between memory arrays and processing resources via buses, leading to inefficiencies even when resources are located on the same chip.
Innovation Solution
The implementation of sensing circuitry within memory arrays that can perform multiplication operations on bit-vectors stored within the array without transferring data via I/O lines, using operations like AND, OR, and SHIFT to reduce computational time and power consumption by enabling parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If data is transferred between memory arrays and processing resources via buses, then multiplication operations can be performed, but power consumption increases and processing time increases
Solution Approach 1:
The patent combines the memory array and processing resources (ALU, FUC) into a single integrated structure where processing units are embedded within the memory array. This merging eliminates the need for separate data transfer buses, allowing multiplication operations to be performed directly on data stored in the memory array, thereby reducing power consumption while maintaining or improving processing efficiency through parallel operation capabilities.
Solution Approach 2:
The patent introduces sensing circuitry as an intermediary component within the memory array that enables direct interaction between stored data and processing units. This intermediary allows data to be processed in-place without requiring transfer to external processing resources, reducing the power and time overhead associated with data movement while enabling efficient multiplication operations.
2Speed
If data is transferred between memory arrays and processing resources via buses, then multiplication operations can be performed, but computational time increases
Solution Approach 1:
By merging processing units with the memory array structure, the patent eliminates data transfer time between separate components. The ALU and FUC are positioned to directly access data within the memory array, enabling immediate processing without bus transfer delays, thus improving computational speed while eliminating data transfer time losses.
Solution Approach 2:
The patent positions processing resources and sensing circuitry within the memory array structure in advance, so that when multiplication operations are needed, the data is already in the optimal location for processing. This preliminary arrangement of processing capabilities within the memory structure eliminates the need for subsequent data transfer, reducing computational time.
3Ease of operation
If external processing resources are used for multiplication operations, then operations can be performed, but device complexity increases due to additional buses and interfaces
Solution Approach 1:
The patent merges processing resources with the memory array to create an integrated structure that reduces device complexity. By combining what would otherwise be separate components (memory array, ALU, FUC, and buses) into a unified architecture, the system eliminates the need for complex external interfaces and data transfer pathways, simplifying the overall device structure while maintaining operational capability.
Solution Approach 2:
The integrated memory-processor structure serves multiple functions simultaneously: data storage, data sensing, and arithmetic processing. This multi-functionality eliminates the need for separate dedicated processing resources and communication buses, reducing device complexity while enhancing operational efficiency through in-place computation.
Data Source
AI summary
Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.