Constant Multiplier Decomposition for Lower-Delay PLD Synthesis
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Solution Overview
Problem
Conventional methods for synthesizing and mapping constant multiplier operations in programmable logic devices (PLDs) lead to increased propagation delay and inefficient resource allocation, resulting in higher clock periods and reduced clock frequencies.
Innovation Solution
The technique involves decomposing constant multiplier operations into efficient arithmetic and logic operations using nearest boundary conditions, such as shift and addition/subtraction operations, to reduce resource consumption and propagation delay, allowing for more efficient implementation in PLDs without analyzing all possible decompositions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional synthesis methods are used for constant multiplier operations, then the implementation is straightforward, but propagation delay increases and resource allocation becomes inefficient
Solution Approach 1:
The constant multiplier operation is segmented into multiple parallel partial product generations. Each partial product is generated independently using logic gates, and then summed using carry-save adders. This segmentation allows concurrent computation of multiple bits, reducing the critical path delay compared to sequential multiplication methods.
Solution Approach 2:
The patent transforms the traditional sequential multiplication approach into a parallel architecture by introducing a new dimensional structure with multiple simultaneous computation paths. The constant multiplier is decomposed into parallel partial product generators and carry-save adder trees, creating a multi-dimensional computational space that reduces time complexity.
2Ease of manufacture
If conventional synthesis methods are used for constant multiplier operations, then implementation is simpler, but configurable resources and interconnections are allocated inefficiently
Solution Approach 1:
The patent applies parameter changes by detecting specific properties of the constant multiplier operand (such as bit patterns, sparsity, or mathematical properties) and automatically selecting from multiple pre-optimized implementation structures. This allows the synthesis tool to transform the same logical function into different physical implementations based on the constant's parameters, optimizing resource usage for each case.
Data Source
AI summary
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation.