Additive Printed Electrical Interconnect Fine Pitch
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Solution Overview
Problem
Traditional printed circuits face challenges in achieving high density and fine line pitch due to issues like taper, carbon contamination, and layer-to-layer shorting, particularly in miniaturization efforts, which affect reliability and electrical performance.
Innovation Solution
A high performance electrical interconnect is developed by merging PCB and semiconductor packaging methods with additive printing technology, using bulk materials and conductive particles or spheres to create vias and circuit geometry, allowing for fine line and high density structures with reduced line and feature pitch, and enabling the incorporation of electrical devices and intelligent functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional PCB fabrication methods are used, then manufacturing process is simple and well-established, but manufacturing precision deteriorates due to taper, carbon contamination, and layer-to-layer shorting in fine line structures
Solution Approach 1:
The patent replaces traditional mechanical PCB fabrication processes (drilling, plating, etching) with additive printing technology. Conductive particles or spheres are deposited layer-by-layer to form vias and circuit geometry, eliminating the mechanical constraints that cause taper, carbon contamination, and shorting in conventional methods. This substitution enables precise control of fine line pitch and via dimensions without the harmful side effects of traditional mechanical fabrication.
2Quantity of substance
If miniaturization is pursued to achieve high density, then circuit density improves, but reliability deteriorates due to taper, carbon contamination, and layer-to-layer shorting
Solution Approach 1:
The patent changes the fundamental parameters of via formation by using additive deposition of conductive particles instead of mechanical drilling and plating. This allows precise control of via diameter, depth, and wall uniformity at high densities without the taper and carbon contamination that plague miniaturized traditional vias. The additive process maintains reliable electrical connections even at sub-1.0 mm pitch by ensuring consistent via geometry and proper conductive material distribution.
3Manufacturing precision
If additive printing technology is used, then manufacturing precision improves for fine line structures, but ease of manufacture deteriorates due to new process requirements
Solution Approach 1:
The patent merges PCB fabrication techniques with semiconductor packaging methods in a hybrid additive printing process. Conductive particles are deposited using printing technology, then subjected to sintering or bonding processes similar to semiconductor packaging. This combination leverages the precision advantages of additive manufacturing while incorporating proven semiconductor-level bonding and sintering techniques to ensure manufacturability and reliable electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables fine contact-to-contact spacing of less than 1.0 mm pitch, reduces parasitic electrical effects, and enhances current carrying capacity, providing superior electrical performance and environmental sustainability compared to traditional methods.
Implementation Method 1
Conductive particles or spheres are deposited in recesses to form circuit geometry
Implementation Method 2
merges processes used in the printed circuit and semiconductor packaging industries with the flexibility of additive printing technology
Data Source
AI summary
A high performance electrical interconnect adapted to provide an interface between terminals on first and second circuit members. The electrical interconnect includes a first circuitry layer with a first surface and a second surface having a plurality of contact pads adapted to electrically coupled with the terminals on the first circuit member. At least one dielectric layer is printed on the first surface of the first circuitry layer. The dielectric layer includes a plurality recesses. A conductive material is deposited in at least a portion of the recesses to create circuit geometry electrically coupled with the first circuitry layer. A second circuitry layer includes a first surface a plurality of contact pads adapted to electrically couple with the terminals on the second circuit member and a second surface attached to the dielectric layers. The circuit geometry electrically couples the first circuitry layer to the second circuitry layer.