Address Comparator Circuit for Memory Read Stability

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Solution Overview

Problem

Consecutive read operations on the same memory cell in memory devices often lead to voltage level reversals and reduced voltage differences between bit lines, causing read failures due to inadequate recovery of bit line voltages.

Innovation Solution

An address comparator circuit is introduced to detect consecutive read commands within a specific number of clock cycles, activating a blocking signal to prevent data transmission between the memory array and external devices when the same memory cell is accessed repeatedly, thereby maintaining voltage levels and preventing read failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If consecutive read operations are performed on the same memory cell, then data access speed is improved, but voltage levels become unstable causing read failures

Engineering Contradiction:

Improvedata access speedVSAvoidread operation reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The address comparator circuit performs preliminary detection of consecutive read commands before the actual read operation completes. When the same address is detected within a predetermined time period, the circuit proactively blocks subsequent data transmission to prevent voltage level reversal, rather than waiting for the failure to occur

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The address comparator circuit acts as an intermediary between the command decoding unit and the data transmission path. It monitors address patterns and inserts a blocking control signal to prevent harmful consecutive read operations, mediating between the need for fast access and the need for stable voltage levels

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If consecutive read commands are executed without blocking, then productivity is improved, but voltage difference between bit lines decreases causing read failures

Engineering Contradiction:

Improveread operation throughputVSAvoidvoltage level reversal

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The address comparator circuit implements feedback by continuously monitoring the sequence of read commands and comparing current addresses with previous ones. When consecutive reads of the same address are detected, the circuit generates a blocking signal that feeds back to prevent further data transmission, creating a closed-loop control system that maintains voltage stability

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The circuit applies preliminary anti-action by detecting the pattern of consecutive read commands and preemptively blocking data transmission before the voltage level reversal can occur. This prevents the harmful effect rather than correcting it after it happens

Inventive Principle:

Principle #9Preliminary anti-action

Data Source

PatentUS9564195B2Address comparator circuit for generating transmission control signal, memory device and memory system including the same

Publication Date: 2017.02.07 SK HYNIX INC

AI summary

An address comparator circuit includes a first determination unit suitable for activating a first control signal when a first address corresponding to a previous read command is identical with a second address corresponding to a current read command; a second determination unit suitable for activating a second control signal when the previous and current read commands are consecutively inputted to the address comparator circuit with an interval of a specific number of clocks or less; and a blocking signal generation unit suitable for generating a blocking signal that blocks data transmission between a memory array and an external device based on the first and the second control signals.