Digital Storage TRIZ Cases

Planarizing barrier material surfaces before metal deposition reduces resistivity by increasing grain size and improving current delivery.

A double-polarity read method applies sequential voltage pulses with alternating polarities to memory cells for accurate logic state detection.

A semiconductor data output path performs pre-toggling operations on output signals to maintain fixed voltage levels at input pads.

A multiplexer-based ternary content addressable memory structure reduces memory cell requirements in programmable logic.

Lateral isolation structures between dual interlocked storage elements reduce radiation-induced multiple-bit upsets by limiting charge sharing.

A memory cell measures electron discharge time through an RC circuit to store multiple bits.

Lowering the reference mat word line drive voltage reduces switching element stress, preventing overstressing while maintaining signal stability.

A shift register circuit uses a boosting unit to raise the gate voltage of a third transistor, enhancing drive capability at high clock frequencies.

A power switch transistor disconnects word line drive power during sleep mode to reduce leakage current in static random-access memory.

Tailored voltage application reduces energy consumption and dielectric breakdown risk in MRAM devices.

A two transistor word line driver uses common gate signals and negative voltage bias to reduce power consumption in memory integrated circuits.

A magnetoelectric spin orbit logic transistor uses a magnetic insulator and transition metal dichalcogenide stack to achieve low gate voltage operation.

Mask signals in a partial write command select specific memory cells, reducing power consumption during sub-cache-line writes.

A semiconductor memory apparatus generates control signals to couple a memory block to a sense amplifier while applying predetermined voltages.

Segmented auto-refresh counting stabilizes internal voltage and prevents misoperation caused by parasitic capacitance between signal lines.

A memory module integrates impedance-matching capacitors between data bus lines and reference voltage to enhance signal integrity.

A sensing circuit uses a feedback amplifier to detect memory cell states.

A pseudo-analog memory computing circuit performs multiply-accumulate operations directly within resistive memory arrays using dynamic weight switching.

A memory controller modifies periodic signal duty cycles and phase to identify optimum settings that minimize data access errors.

An address comparator circuit detects consecutive read commands to activate a blocking signal that controls data transmission between the memory array and external devices.

Internal refresh control circuits manage timing to reduce power consumption while maintaining data integrity.

A reference resistance setting unit selects column and row lines to generate a stable reference value for resistive memory cells.

Regional clock fabric provides distinct signal speeds to FPGA regions, resolving flexibility versus complexity trade-offs.

Automated discovery scans update performance data collection configurations when I/O paths change, eliminating manual reconfiguration errors.

A pseudo static random access memory controller provides multiple page starting addresses to enable continuous burst operations.

Segmenting the memory array into domains allows selective activation via a selector device, lowering power consumption while maintaining read access times.

Segmenting DDR and NVM regions within a hybrid DIMM manages thermal dissipation while increasing storage capacity.

A semiconductor storage device uses a switch with continuously varying conduction between memory cells and sense amplifiers.

Memory control circuit dynamically adjusts sampling points using multiple delay units to maintain optimal data capture accuracy.

A dummy line with lower resistance reduces source line impedance differences, improving data sensing margin without trimming processes.

A DDR memory write circuit counts data strobe cycles to initiate operations internally within the strobe domain.

One sense amplifier amplifies two bit line pairs using share control signals, reducing area loss and increasing integration density.

Mini-gaps act as local sensors between array sections to amplify data signals through parallel interconnect layers.

An internal negative voltage generation device uses an initial driving block to stabilize word line voltages.

Dynamic adjustment of read current and pulse width balances read sense margin against read disturb bit error rates under varying thermal conditions.

A semiconductor memory device generates data training patterns to adjust clock phases for synchronization.

A semiconductor device generates an interruption signal to block redundant refresh operations when target addresses match active memory locations.

Series resistors at cross-points compensate for parasitic voltage drop, enabling larger resistive processing unit arrays without high resistance devices.

A hybrid sensing scheme merges current and voltage measurements to stabilize PCRAM resistance states.

Vertical stacking of transistor gates above storage devices increases integration density without expanding the horizontal area occupied by memory cells.

Column-wise sense amplifiers equalize signal transmission distances to eliminate read speed variations across memory cell rows.

Dynamic voltage scaling regulates channel bit-error-rate by adjusting power levels, resolving the trade-off between reliability and energy consumption.

A power detector circuit generates an isolation signal to disable the clock generator in dual rail SRAMs.

A memory device floats word and bit lines after pre-charge to reduce capacitance.