Memory Array Domain Segmentation for Read Power Reduction
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Solution Overview
Problem
Current memory arrays face challenges in reducing power consumption while maintaining read access times and increasing capacity, often requiring tradeoffs that result in higher power consumption or longer access times due to issues like full-scale signal swings on high capacitance bit lines and destructive read processes.
Innovation Solution
The implementation of a memory array architecture with multiple domains, a current controller, and a selector device, along with bit line amplifier units and a reference monitor, which controls bit cell current and voltage to selectively connect memory domains, reducing power consumption and improving read access times by canceling threshold voltages and minimizing voltage transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capacity is improved, but power consumption increases
Solution Approach 1:
The memory array is divided into multiple domains (first domain, second domain, etc.) that can be selectively activated. The selector device enables only the required domain to be connected to the current controller, allowing high-capacity storage while consuming power only for active domains rather than the entire array.
2Speed
If read access time is reduced, then speed is improved, but power consumption increases
Solution Approach 1:
By segmenting the memory array into domains and selectively activating only the required domain during read operations, the system achieves fast access times for active domains while minimizing power consumption by keeping other domains in a low-power state.
Solution Approach 2:
The selector device periodically connects different domains to the current controller based on read requirements. This periodic activation allows the system to maintain fast access times for active domains while reducing overall power consumption through intermittent operation of different domain segments.
Data Source
AI summary
An electronic memory array includes a plurality of memory domains, a current controller, and a selector device. Each memory domain includes a plurality of bit cells. The current controller includes a current controller output electrically connectable to said plurality of memory domains and is configured to control a bit cell current. The selector device is electrically connected to the current controller and the plurality of memory domains. The selector device is configured to selectively electrically connect the current controller output to only a select one of said memory domains, such that the current controller controls only the bit cell current of the bit cells of the select memory domain.