Low Voltage Memory Sensing Circuit with Feedback Amplifier
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Solution Overview
Problem
Conventional memory cells with reduced scales and low supplied voltage struggle to accurately transition between program and erase states, leading to failure in distinguishing these states due to insufficient voltage differences required for transistor switching.
Innovation Solution
A sensing circuit comprising a sensing stage with a first P-type MOSFET and a first N-type MOSFET, connected to a memory cell, utilizing an inverter to indicate program or erase states through voltage changes, and including an amplifier stage, reference transistor, reset transistor, and read enabling stage to manage voltage and current for accurate state detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the memory cell scale is reduced to decrease area, then the supplied voltage Vdd must be lowered, but the voltage difference (Vdd-Vthp) becomes insufficient to switch transistors reliably
Solution Approach 1:
The patent introduces a sensing circuit as an intermediary between the memory cell and the read logic. This sensing circuit includes a sense amplifier that can operate with reduced voltage margins, effectively mediating the signal transition even when Vdd-Vthp is small. The sense amplifier boosts the small voltage differences produced by the scaled-down memory cell, enabling reliable state detection without requiring large voltage swings that would demand higher supply voltages.
Solution Approach 2:
The patent changes the operating parameters of the sensing circuit to accommodate low voltage operation. Specifically, the sense amplifier is designed with adjusted threshold voltages and gain characteristics that allow it to function reliably at lower supply voltages. This parameter adjustment enables the circuit to maintain adequate noise margins and switching reliability even when the supply voltage headroom is limited by scaled-down memory cell requirements.
2Device complexity
If conventional latch circuits are used for state detection, then the circuit structure is simple, but the voltage requirements prevent reliable operation at low supplied voltage
Solution Approach 1:
The sensing circuit incorporates feedback mechanisms where the output of the sense amplifier is fed back to control the sensing transistors. This feedback loop ensures that the sensing circuit maintains proper operation even with reduced voltage margins. The feedback stabilizes the operating point and ensures that the sense amplifier can reliably distinguish between program and erase states despite the limited voltage headroom available in scaled-down memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise differentiation between program and erase states in memory cells with low power supply, overcoming voltage limitations and ensuring reliable operation by using a feedback loop and power-saving mechanisms, thus avoiding operational failures.
Implementation Method 1
The first P-type MOSFET has a gate connected to a memory cell for sensing an output current of the memory cell. The first N-type MOSFET has a drain connected to a drain of the first P-type MOSFET, and having a source connected to ground.
Implementation Method 2
The inverter has an input terminal connected to the drain of the first N-type MOSFET. A voltage at an output terminal of the inverter is used for indicating a program state or an erase state of the memory cell.
Data Source
AI summary
An output current of a memory cell is sensed by a sensing circuit for distinguishing a program state and an erase state of the memory cell. The sensing circuit includes a reference transistor, a P-type MOSFET, and an N-type MOSFET. The P-type MOSFET has a gate connected to a memory cell for receiving an output current of the memory cell. The N-type MOSFET has a drain connected to a drain of the first P-type MOSFET, and has a source connected to ground. The inverter has an input terminal connected to the drain of the first N-type MOSFET. The voltage at an output terminal of the inverter is used for indicating the program state or the erase state of the memory cell. The reference transistor has a gate connected to a reference signal, and has a drain connected to the gate of the P-type MOSFET.