Pseudo-analog Memory Computing Circuit for AI Multiply-Accumulate Operations
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Solution Overview
Problem
Conventional computer architectures are limited by the transmission speed of buses, making them unsuitable for AI circuits that require fast multiply-accumulate operations, and NOR flash memory struggles with multi-level cells and scaling trends, limiting computation ability and area efficiency.
Innovation Solution
A pseudo-analog memory computing circuit with input and output circuits and pseudo-analog memory computing units that use digital-to-analog and analog-to-digital converters, along with resistors and switches, to perform computations within the memory, allowing for variable weights and multi-layer computations without the need for additional circuits, utilizing magnetoresistive or resistive random access memory for weight storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional computer architecture is used, then data transmission via bus is simple, but computation ability is limited by transmission speed
Solution Approach 1:
The computing circuit merges the computation function with the memory function into a single integrated unit. The memory array directly performs multiply-accumulate operations on input signals without requiring data to be transmitted to a separate processor, thereby eliminating the bottleneck of bus transmission speed while maintaining high computation ability.
Solution Approach 2:
The patent introduces an intermediary computing circuit within the memory that performs computations using analog current signals. This intermediary computing unit processes data locally within the memory array, avoiding the need for high-speed data transmission to an external processor while achieving fast computation results.
2Productivity
If multiple computing circuits are used for multi-layer computation, then computation ability is improved, but memory area increases
Solution Approach 1:
The patent implements dynamic weight switching within a single computing circuit. By using switchable resistive memory elements that can change their resistance values based on control signals, the same physical circuit can perform different computations with different weight configurations, eliminating the need for multiple dedicated computing circuits for different layers or weight sets.
Solution Approach 2:
The computing circuit is designed as a universal unit that can perform multiple computation functions. The same memory array and computing circuit structure can be reused for different layers of computation by dynamically reconfiguring the weight values through control signals, making a single circuit serve multiple computational purposes.
3Ease of manufacture
If NOR flash memory is used for weight storage, then data storage is simple, but multi-level cells are hard to realize
Solution Approach 1:
The patent uses resistive memory elements whose resistance values can be dynamically changed by applying different voltage or current patterns. These resistive memory elements can achieve multiple discrete resistance states (multi-level cells) to store different weight values, providing both manufacturing simplicity and versatile multi-level storage capability through parameter changes in the resistance state.
Data Source
AI summary
A pseudo-analog memory computing circuit includes at least one input circuit, at least one output circuit and at least one pseudo-analog memory computing unit. Each pseudo-analog memory computing unit is coupled between one of the at least one input circuit and one of the at least one output circuit and has at least one weight mode. Each pseudo-analog memory computing unit generates at least first computing result for a coupled output circuit according to a weight of a selected weight mode and at least one input signals of a coupled input circuit.