Semiconductor Memory Sense Amplifier Area Reduction
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face challenges in achieving high integration due to the wide area occupied by sense amplifiers and inefficient spatial utilization, as they require the same number of sense amplifiers as bit line pairs, leading to extra space and reduced area margin.
Innovation Solution
The semiconductor memory apparatus incorporates a configuration where one sense amplifier can amplify two bit line pairs, utilizing share control signals to connect and control the amplification of bit lines, reducing the number of sense amplifiers needed and minimizing area loss by optimizing the arrangement of sense amplifiers and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same number of sense amplifiers as bit line pairs is used, then each bit line pair can be amplified independently, but the area occupied by sense amplifiers increases and integration is reduced
Solution Approach 1:
The patent combines two bit line pairs (first bit line pair and second bit line pair) into a single sense amplifier. The sense amplifier includes a first amplification unit for amplifying the first bit line pair and a second amplification unit for amplifying the second bit line pair, allowing one sense amplifier to handle multiple bit line pairs simultaneously, thereby reducing the total number of sense amplifiers and the area they occupy.
Solution Approach 2:
The sense amplifier is designed with multi-functional capability to amplify multiple different bit line pairs. By including multiple amplification units within a single sense amplifier structure, the device can serve multiple functions (amplifying first bit line pair, second bit line pair, etc.) that would traditionally require separate dedicated amplifiers, thus improving area utilization.
2Area of stationary object
If sense amplifiers are arranged to connect to multiple bit line pairs, then area is reduced, but connection complexity and control difficulty increase
Solution Approach 1:
The sense amplifier is segmented into distinct amplification units, where each unit is responsible for amplifying a specific bit line pair. The first amplification unit handles the first bit line pair while the second amplification unit handles the second bit line pair. This segmentation allows for modular design that simplifies the internal structure and control logic despite handling multiple bit line pairs.
Solution Approach 2:
The patent introduces a bit line pair selecting unit that acts as an intermediary between the multiple bit line pairs and the amplification units. This selecting unit receives column selection signals and determines which bit line pairs should be connected to which amplification units, thereby simplifying the control logic and reducing the complexity of direct connections between sense amplifiers and multiple bit line pairs.
3Reliability
If more sense amplifiers are used, then bit line amplification performance is improved, but spatial efficiency and integration density decrease
Solution Approach 1:
Multiple amplification functions are merged into a single sense amplifier structure. The first amplification unit and second amplification unit are integrated within the same sense amplifier, allowing the device to maintain high amplification performance for multiple bit line pairs while occupying the area of only one sense amplifier, thus improving integration density.
Solution Approach 2:
The sense amplifier is designed as a universal amplification device that can amplify any of the bit line pairs assigned to it. By making the sense amplifier multi-functional rather than dedicated to a single bit line pair, the system achieves both high amplification performance and high integration density, as fewer sense amplifiers are needed to cover the same number of bit line pairs.
Data Source
AI summary
A semiconductor memory includes a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first bit line equalize signal; a column selecting unit configured to connect the positive sensing line and the negative sensing line to a first data bus and a second data bus, respectively, in response to a column selection signal; and a share control unit configured to connect the positive sensing line and a positive first bit line of the first bit line pair or a positive second bit line of the second bit line pair in response to a second bit line equalize signal, a positive share control signal and a negative share control signal.