Memory Module Impedance Matching Capacitor Signal Integrity

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Solution Overview

Problem

Conventional memory systems face signal integrity degradation due to impedance mismatching between semiconductor memory devices and memory controllers, despite the use of stub resistors to improve signal integrity, as shown by significant impedance distance from the matching point at high frequency operations.

Innovation Solution

Incorporating impedance-matching capacitive elements, such as capacitors, between data bus lines and a reference voltage within each memory module to enhance signal integrity by improving impedance matching, which can also include stub resistors for further control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If stub resistors are used to improve signal integrity, then signal integrity is improved, but impedance mismatching remains due to data bus and semiconductor memory device impedance

Engineering Contradiction:
Improvesignal integrityVSAvoidimpedance matching complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A capacitor is introduced as an intermediary component between the data bus and ground to form an RC circuit with the stub resistor. This capacitor acts as a mediator that adjusts the impedance characteristics of the data bus, enabling better impedance matching between the memory module and memory controller without requiring complex circuit redesigns.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the electrical parameters of the data bus by adding a capacitor, which modifies the impedance characteristics. By adjusting the capacitor value, the impedance of the data bus can be tuned to match the memory controller's input impedance, thereby improving signal integrity through parameter optimization rather than structural complexity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If operating speed is increased to improve data transmission speed, then productivity is improved, but signal integrity degrades at high frequency operations

Engineering Contradiction:
Improvedata transmission speedVSAvoidsignal integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The capacitor is placed in advance on the data bus to preemptively counteract the impedance mismatching that would occur at high frequencies. By having the RC circuit already in place before high-speed operations begin, the system proactively prevents signal integrity degradation rather than attempting to correct it after the fact.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The capacitor serves as a frequency-dependent intermediary that becomes increasingly effective at higher frequencies. It mediates between the data bus and ground, providing a frequency-dependent impedance that compensates for the increasing signal integrity issues that arise at higher operating speeds.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively reduces signal distortion and improves signal integrity by bringing impedance closer to a matching point, resulting in larger eye openings and reduced signal skew during both read/write and on-die termination operations, compared to conventional systems.

Implementation Method 1

improving signal integrity (SI) by including a capacitor for impedance matching on a data bus

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS7420818B2Memory module having a matching capacitor and memory system having the same
Publication Date: 2008.09.02 SAMSUNG ELECTRONICS CO LTD
  • US7420818B2 patent drawing
  • US7420818B2 patent drawing
  • US7420818B2 patent drawing

AI summary

A memory module includes: one or more semiconductor memory devices; a plurality of module tabs configured to transmit and receive signals between the one or more semiconductor memory devices and external devices; a data bus configured to transfer signals between data input/output pins of the one or more semiconductor memory devices and the plurality of module tabs; and impedance-matching capacitive elements, each coupled between a line of the data bus and a reference voltage. Accordingly, the memory module and a memory system employing such a module can achieve improved impedance matching, thereby also improving signal integrity.