Storage Circuit Variable Resistance Sense Amplifier Read Speed

The patent divides the reference circuit into multiple segments, with each column having its own dedicated reference cells arranged in m rows. This segmentation ensures that each memory cell row has a corresponding reference cell at the same physical location, equalizing signal transmission distances and eliminating read speed variations across different rows while maintaining efficient circuit organization.

The patent transitions from a shared reference circuit architecture (one reference row for multiple memory rows) to a distributed reference circuit architecture (m reference rows corresponding to m memory rows). This dimensional reorganization in the circuit layout ensures that reference signals travel equal distances regardless of which memory row is being read, thereby achieving uniform read speeds across all columns.

The patent extracts the bit line and reference line connections from the drain terminals and relocates them to the gate terminals of the sense amplifier transistors. This extraction removes the large capacitive loads that would otherwise be present at the drain nodes, significantly reducing the time required to charge and discharge these lines and thereby accelerating sense amplifier operation while maintaining circuit simplicity.

The patent changes the electrical connection parameters of the sense amplifier by switching from drain-received signals to gate-received signals. This parameter change fundamentally alters the input impedance and loading characteristics, transforming the sense amplifier into a high-speed differential comparator that can quickly detect resistance changes in memory cells without being burdened by line capacitance.