DRAM Refresh Control Circuit Preventing Duplicate Address Operations
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face data loss due to varying electric charges in cell capacitors, leading to malfunction, especially with increased integration that causes interference between memory cells and word lines, necessitating an effective refresh operation to prevent data loss.
Innovation Solution
A semiconductor device incorporating a period signal generation circuit, an interruption signal generation circuit, a target address generation circuit, and a control signal input circuit to manage refresh operations by setting target addresses and preventing duplicate refreshes, thereby optimizing the refresh process and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between memory cells and word lines is reduced to increase integration, then device density is improved, but interference between adjacent memory cells and word lines increases causing data loss
Solution Approach 1:
The patent implements a preliminary address comparison operation before executing the refresh operation. The interruption signal generation circuit compares the target address with the active address in advance, and generates an interruption signal if they match, preventing the refresh operation from proceeding. This preliminary check eliminates the harmful interference effect before it can occur.
Solution Approach 2:
The patent introduces an interruption signal as an intermediary control mechanism between the address matching detection and the refresh operation execution. This intermediary signal acts as a mediator that blocks the harmful refresh operation when address matching is detected, while allowing normal operation when addresses differ.
2Reliability
If refresh operations are performed for all addresses to prevent data loss, then data integrity is improved, but power consumption increases due to duplicate refresh operations
Solution Approach 1:
The patent implements a feedback mechanism where the interruption signal generation circuit continuously monitors and compares the target address with the active address, and uses this feedback information to control whether the refresh operation should proceed. When addresses match, the feedback loop generates an interruption signal that prevents the refresh operation, thereby eliminating duplicate operations and reducing power consumption while maintaining data integrity.
Data Source
AI summary
A semiconductor device includes a period signal generation circuit and an interruption signal generation circuit. The period signal generation circuit generates a period signal in response to a refresh pulse and an end pulse. The interruption signal generation circuit generates an interruption signal for controlling an operation that an address is set as a target address, if the address having the same logic level combination as the target address is inputted while the period signal is enabled.