Nonvolatile Memory Reference Cell Array for Multi-Level Data Detection

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Solution Overview

Problem

Existing nonvolatile memory devices using resistive memory cells face challenges in accurately reading and writing multi-level data due to the need for multiple reference currents or voltages, which complicates the detection of resistance distributions and data storage.

Innovation Solution

A nonvolatile memory device with a reference resistance setting unit that selects a subset or all of the column and row lines to set a reference resistance value, allowing for accurate data detection by comparing the resistance values of memory cells in the normal cell array with reference resistance values generated from the reference cell array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple reference currents or voltages are used to accurately detect multi-level data, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvedata detection accuracyVSAvoidreference cell configuration complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The memory cell array is divided into multiple sub-arrays, with dedicated reference cells allocated to each sub-array. This segmentation allows each reference cell to serve a specific sub-array, simplifying the overall reference cell configuration while maintaining the capability to accurately detect multi-level data across the entire memory array.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If reference cells are kept changing to generate reference currents for reading data, then adaptability is improved, but reliability deteriorates due to instability in resistance status

Engineering Contradiction:
Improvereference current generation flexibilityVSAvoidreference resistance stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

Reference cells are pre-configured with specific resistance values during manufacturing or initialization. These pre-set reference cells maintain stable resistance status and are selected based on the read operation requirements, rather than dynamically changing reference cells. This preliminary configuration ensures both adaptability for different read operations and reliability through stable resistance values.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances the accuracy of read operations by providing a consistent reference resistance value, reducing mismatch between read and reference currents/voltages and improving the reliability of data storage in multi-level cells.

Implementation Method 1

The resistive memory device includes a memory cell made of variable resistive material, where the memory cells variable resistance depends on the amount of current running through the material.

Methodology Applied
Scientific EffectVariable resistive material effect: Electrical Resistance

Implementation Method 2

a reference resistance setting unit configured to enable a subset or all of the column lines and row line to set a reference resistance value

Methodology Applied
Scientific EffectElectrical resistance measurement: Electrical Resistance

Data Source

PatentUS9214227B2Nonvolatile memory device performing read operation using reference cell array and semiconductor system using the same
Publication Date: 2015.12.15 SK HYNIX INC
  • US9214227B2 patent drawing
  • US9214227B2 patent drawing
  • US9214227B2 patent drawing

AI summary

Provided is a nonvolatile memory device including a resistive memory cell and semiconductor system using the same that is capable of setting the reference resistance value using resistance values of a plurality of memory cells. The nonvolatile memory device comprises one or more column lines, two or more row lines, a plurality of memory cells configured to be connected to the column lines and each of the row lines, and a reference resistance setting unit configured to enable a subset or all of the column lines and row lines and to set a reference resistance value.