SRAM Sleep Mode Leakage Control via Power Switch Transistor
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Solution Overview
Problem
Current SRAM designs face challenges in reducing leakage power consumption without increasing layout size, especially in large-capacity SRAMs, due to the need for large CMOS transistors in power supply modules and strict timing requirements for entering and exiting data retention mode.
Innovation Solution
The implementation of a sleep mode control module with a word line drive power supply module that includes a power switch transistor, allowing for controlled power supply to the word line driver, which disconnects power during sleep mode to eliminate leakage paths and reconnects during normal operation, enabling flexible and quick mode transitions without strict timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dual power supplies and power switch modules are introduced to enable data retention mode, then leakage reduction and data retention are achieved, but circuit complexity and layout area increase significantly
Solution Approach 1:
The patent extracts the power supply control function from the traditional dual power supply architecture by using a single power supply VDD with a power switch transistor (PMOS) that selectively connects or disconnects power to the memory cell array. This eliminates the need for separate peripheral and memory power supplies, reducing circuit complexity while maintaining leakage reduction capability.
Solution Approach 2:
The power switch transistor serves multiple functions: it acts as a power supply switch for leakage reduction, a reset switch for data initialization, and a control element for mode switching between active and retention states. This multi-functionality reduces the need for additional dedicated circuits.
2Reliability
If large-sized CMOS transistors are introduced to ensure power supply stability, then power supply stability is improved, but layout area expands by more than 50%
Solution Approach 1:
The patent changes the transistor size parameters by using appropriately sized PMOS and NMOS transistors in the power switch and memory cell structures. The power switch PMOS is sized to provide sufficient drive capability for stable power supply, while the memory cell transistors are optimized for area efficiency. This parameter optimization achieves power supply stability without excessive area expansion.
3Reliability
If strict timing requirements are enforced for entering and exiting data retention mode, then current surge prevention is achieved, but state switching time increases and operational flexibility decreases
Solution Approach 1:
The patent implements dynamic control of the power switch transistor through the RWCTRL signal, which can be adjusted in real-time based on operational requirements. The switch transitions smoothly between connected and disconnected states, allowing flexible timing adjustments without causing current surges. This dynamic control enables adaptive operation while preventing harmful current spikes.
4Loss of energy
If power switch modules and control modules are added to achieve leakage reduction, then leakage control function is implemented, but layout area increases
Solution Approach 1:
The patent merges the power switch control functionality with the existing word line control structure by using the same RWCTRL signal to control both the power switch PMOS and the word line driver. This integration eliminates the need for separate control logic modules, achieving leakage reduction without significant area increase.
Data Source
AI summary
The present application discloses a static random-access memory. Upon an entry to a sleep mode, a power switch transistor in a word line drive power supply module is off, thus controlling the elimination of a leakage path of a word line driver, so that leakage power consumption of the SRAM is maintained at that of an on standby state of a normal operating mode or a data retention mode. The entry to and exit from the sleep mode of the SRAM can be carried out flexibly and quickly, without complying with strict timing requirements required by stepwise powering-on and stepwise powering-off, thereby facilitating the implementation of a leakage control function without increasing a layout size. The present application discloses an integrated circuit layout of the static random-access memory.