Memory Cell Isolation Structure Mitigating Charge Sharing
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Solution Overview
Problem
Radiation-induced bit flips and multiple-bit upsets in semiconductor memory devices cause data errors, which existing radiation hardening techniques struggle to fully mitigate, especially as feature sizes shrink, leading to increased susceptibility to charge sharing effects.
Innovation Solution
Incorporating an isolation structure, such as a p-n junction or shallow trench isolation, between memory cells to limit charge sharing and reduce the occurrence of multiple-bit upsets, while using dual interlocked storage cells (DICE cells) that can self-correct data errors due to single radiation events by storing complementary data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are shrunk to increase integration density, then productivity and storage capacity are improved, but susceptibility to charge sharing effects and radiation-induced errors increases
Solution Approach 1:
The memory device is segmented into multiple storage elements (first and second storage elements) that are interlocked and coupled together. Each storage element contains storage nodes that store complementary data, creating a divided structure that prevents charge sharing from affecting the entire memory cell simultaneously. This segmentation allows higher integration density while mitigating radiation susceptibility.
Solution Approach 2:
An intermediate structure is introduced between the first and second storage elements to couple their outputs and inputs. This intermediate coupling mechanism ensures that charge generated by radiation events in one storage element does not directly affect the other storage element, thereby preventing charge sharing while maintaining functional integration at high density.
2Device complexity
If conventional memory cell structures are used, then device complexity is low, but multiple-bit upsets occur due to charge sharing between adjacent cells
Solution Approach 1:
The first and second storage elements are merged into an interlocked structure where they share common input and output nodes. This merging creates a unified memory cell structure that maintains low device complexity while the interlocked design ensures that radiation-induced charge in one element cannot flip bits in the other element, thereby preventing multiple-bit upsets and improving data accuracy.
Solution Approach 2:
The storage elements use homogeneous complementary data storage (same data stored in both elements with identical coupling mechanisms), which simplifies the overall structure and reduces device complexity. This homogeneity ensures that both storage elements respond identically to radiation events, making the system more predictable and reliable while maintaining structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces both single and multiple-bit upsets, enhancing the reliability of memory devices by limiting charge sharing and enabling self-correction of data errors, thus improving the functionality of electronic systems that rely on these memory elements.
Implementation Method 1
An isolation element in the substrate is arranged laterally (e.g., in parallel to wafer surface) between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements.
Data Source
AI summary
One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.