Internal Negative Voltage Generation for Memory Cell Data Retention
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Solution Overview
Problem
Conventional internal negative voltage generation devices in semiconductor memory devices suffer from variations in negative word line driving voltage due to dynamic power consumption, leading to degraded data maintenance ability of memory cells.
Innovation Solution
An internal negative voltage generation device that includes a first internal negative voltage generation block to generate a voltage lower than ground, a second internal negative voltage generation block to generate a voltage higher than the first but lower than ground, and an initial driving block to drive the second voltage during specific time intervals, ensuring a stable negative word line driving voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a negative word line scheme is adopted to reduce off leakage, then data maintenance ability is improved, but voltage stability deteriorates due to dynamic power consumption variations
Solution Approach 1:
The patent applies preliminary action by pre-charging the word line to a negative voltage level before the actual read/write operation. The initial driving block generates a negative word line driving voltage in advance, and the word line is precharged to this negative level during a precharge period before the active operation begins. This preliminary negative voltage preparation ensures that when the memory cell transistor is turned off during the active operation, the gate-source voltage relationship already establishes the conditions to minimize off leakage current, thereby improving data maintenance ability while managing voltage stability through controlled timing
Solution Approach 2:
The patent implements periodic action through the oscillating unit that generates periodic oscillation signals to drive the charge pump circuit. The charge pump operates in periodic cycles, switching between charging and discharging phases to generate the required negative voltage. Additionally, the word line undergoes periodic precharging to negative voltage followed by active operations, creating a rhythmic pattern of voltage application that maintains stable operation while reducing off leakage effects during critical data retention periods
2Reliability
If the threshold voltage of memory cell transistor is increased to reduce off leakage, then data retention is improved, but storage time period increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the gate voltage parameter rather than permanently increasing the threshold voltage. The initial driving block changes the operating parameter (gate voltage) to a negative level during precharge and active operations. This temporary parameter modification reduces off leakage current without permanently altering the transistor's threshold voltage, thereby maintaining fast write speeds and short storage time periods while achieving improved data retention during critical operations
Solution Approach 2:
The patent implements preliminary anti-action by applying a negative voltage to the word line in advance of the active operation to counteract the potential off leakage effect. This preliminary negative bias creates an opposing electrical field that prevents charge leakage from occurring in the first place during the subsequent active operation. By anticipating and counteracting the leakage mechanism before it can affect data integrity, the system achieves reliable data retention without needing to increase threshold voltage or extend storage time periods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution minimizes variations in the negative word line driving voltage, thereby reducing off-leakage current and improving the data maintenance ability of memory cells.
Implementation Method 1
The pumping unit 116 is configured to perform a pumping operation in response to the oscillation signal OSC outputted from the oscillating unit 114 and to generate the back-bias voltage VBB in accordance with the pumping operation. The pumping unit 116 may be implemented as a negative charge pump.
Implementation Method 2
The voltage detection unit 112 is configured to compare a first reference voltage VR_VBB with a fed-back voltage of the back-bias voltage VBB and to output a detection signal DET as the comparison result.
Implementation Method 3
The driving unit 124 is implemented as an NMOS transistor coupled between a back-bias voltage (VBB) terminal and a negative word line driving voltage (VBBW) terminal, the NMOS transistor receiving the driving control signal DRV outputted by the voltage comparison unit 122 through a gate thereof.
Data Source
AI summary
An internal negative voltage generation device includes a first internal negative voltage generation block configured to generate a first internal negative voltage which is lower than a ground voltage; a second internal negative voltage generation block configured to generate a second internal negative voltage according to the first internal negative voltage, the second internal negative voltage being higher than the first internal negative voltage and lower than the ground voltage; and an initial driving block configured to additionally drive a second internal negative voltage terminal to the first internal negative voltage during an initial set time interval of an active operation time interval.