Semiconductor Storage Device With Variable Conduction Switch

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Solution Overview

Problem

As memory capacity increases and process refinement reduces load capacitance, the sense amplifier power supply struggles to adapt to peak current during charging and discharging of bit lines, leading to increased amplification time and access time challenges in semiconductor storage devices.

Innovation Solution

Incorporating a switch with continuously variable conduction between memory cells and sense amplifiers, controlled by a switch control circuit, to optimize the conduction state during sense amplifier operations, thereby reducing access time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of memory cells connected to bit lines is increased to enhance memory capacity, then the memory capacity is improved, but the peak current during charging and discharging of bit lines increases, causing the sense amplifier power supply to struggle to adapt and leading to increased amplification time

Engineering Contradiction:
Improvememory capacityVSAvoidamplification time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the transfer gate's conduction state adjustable rather than fixed. The transfer gate can dynamically switch between different conduction states (fully conductive, partially conductive, fully non-conductive) based on the operational phase, allowing the system to adapt to varying current demands and reduce peak current impacts on the sense amplifier power supply during amplification.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of gate voltage applied to the transfer gate to control its conduction characteristics. By varying the gate voltage between different levels (e.g., VDDA, VPP, VSS), the transfer gate's conductance is modified to optimize the balance between memory cell connection and sense amplifier load, thereby managing peak current and reducing amplification time.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If the load capacitance of memory cells is decreased in conjunction with process refinement, then the manufacturing process is improved, but the number of memory cells to be connected to bit lines must be increased, which exacerbates the peak current problem and increases access time

Engineering Contradiction:
Improveprocess refinementVSAvoidaccess time
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The dynamic control of the transfer gate's conduction state allows the system to compensate for increased cell density. By adjusting the transfer gate's conductance in real-time during operations, the patent manages the effective load on bit lines, reducing peak current demands and maintaining acceptable access times despite higher memory cell density and decreased individual cell capacitance.

Inventive Principle:
Principle #15Dynamics

3Speed

If the transfer gate is placed in OFF state at the start of sense latching to withdraw load capacitance, then the bit line can be rapidly amplified, but the connection between sense amplifier and memory cell is broken, requiring additional time to restore connection

Engineering Contradiction:
Improvebit line amplification speedVSAvoidconnection restoration time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent applies dynamics by using a transfer gate with continuously adjustable conduction rather than a simple ON/OFF switch. The transfer gate can be set to partially conductive states, allowing the system to gradually restore connection between the sense amplifier and memory cell while maintaining stable bit line amplification, thereby eliminating the need for complete disconnection and subsequent restoration.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7782696B2Semiconductor storage device
Publication Date: 2010.08.24 LAPIS SEMICON CO LTD
  • US7782696B2 patent drawing
  • US7782696B2 patent drawing
  • US7782696B2 patent drawing

AI summary

The semiconductor storage device according to the present invention comprises a switch provided to a bit line between a memory cells and a sense amplifier and capable of continuously varying a degree of conduction; and a switch control circuit for varying the degree of conduction of the switch in accordance with an access request signal. The semiconductor storage device of the present invention enables operation in which the degree of conduction between the sense amplifier and a memory cell is increased, and an ON state is achieved during a time in which the sense amplifier amplifies the holding voltage of the memory cell and feeds the amplified holding voltage to the bit line. The access time can thereby be reduced.