Multi-level Memory Cell Using Electron Discharge Time Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory cells face limitations in storing multiple bits due to the limited spectrum width of physical parameters, leading to accuracy issues in programming and reading characteristic parameters, especially as the number of levels increases, with factors like electrical noise and sense voltage disturbances interfering with data representation.
Innovation Solution
A method where the effective resistance of a memory cell, formed by a resistor-capacitor circuit, is used to vary electron discharge times, allowing for the representation of multiple binary values by associating each value with a target discharge time, enabling accurate reading and writing through pre-charging and measuring electron discharge times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored in a single memory cell by increasing the number of levels, then the storage capacity is improved, but the measurement precision deteriorates due to electrical noise and sense voltage disturbance
Solution Approach 1:
The patent changes the measurement parameter from voltage to time delay. Instead of measuring voltage levels directly (which is susceptible to noise), the system measures the time delay in electron discharge through an RC circuit. This parameter transformation fundamentally resolves the measurement precision issue while maintaining multi-level storage capability.
Solution Approach 2:
The patent replaces the electrical measurement system (voltage-based) with a temporal measurement system (time-based). By substituting voltage measurement with time delay measurement, the system eliminates the harmful effects of electrical noise and sense voltage disturbance that plague traditional multi-level memory reading operations.
2Quantity of substance
If the spectrum width of physical parameters is increased to accommodate more levels, then the storage capacity is improved, but the reliability deteriorates due to interference from electrical noise and sense voltage disturbance
Solution Approach 1:
The patent transforms the physical parameter used for data representation from voltage (which is noisy and unreliable at multiple levels) to time delay (which is inherently more reliable). The time delay parameter is derived from the discharge characteristics of an RC circuit, providing a stable and noise-resistant measurement basis for multi-level storage.
3Device complexity
If traditional voltage-based multi-level storage is used, then the device complexity is reduced, but the manufacturing precision deteriorates due to difficulty in programming and reading characteristic parameters
Solution Approach 1:
The patent changes the characteristic parameter from voltage to time delay, which fundamentally improves programming and reading precision. The time delay parameter provides clearer distinction between levels and is less susceptible to manufacturing variations, thereby improving manufacturing precision without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable and accurate storage and retrieval of multiple bits in a single memory cell by minimizing perturbation during read/write processes, effectively addressing the limitations of spectrum width and noise interference.
Implementation Method 1
the time required for voltage to be discharged through an electronic circuit formed, at least partially, by the memory cell
Implementation Method 2
electron discharge times within a memory cell through an intrinsic resistor-capacitor circuit
Data Source
AI summary
A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.