Vertically Stacked Transistors for High-Density Memory Cells
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Solution Overview
Problem
Existing microelectronic device designs face challenges in increasing integration density and performance while maintaining compactness and simplified designs, particularly in memory devices where increasing the number of transistors or capacitance leads to increased area and decreased packing density.
Innovation Solution
The proposed solution involves a microelectronic device structure that includes a first die with an array region of memory cells, each comprising a pair of transistor structures and a storage device vertically overlying them, along with peripheral regions containing sub-word line driver circuitry. A second die vertically overlies the first, incorporating sense amplifier regions and additional CMOS regions, which facilitates a higher density of memory cells in a smaller horizontal area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of transistors per memory cell is increased, then the operating parameters of the memory cell are improved, but the area occupied by the memory cell increases and packing density decreases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertical architecture. Multiple transistor gates are stacked vertically above the storage device, allowing multiple transistors to occupy a smaller horizontal footprint while maintaining improved operating parameters through enhanced control over the storage device.
Solution Approach 2:
The patent implements a nested structure where multiple transistor gates are vertically stacked and positioned above the storage device. This nesting arrangement allows the transistor structures to be contained within a compact vertical space, improving packing density while maintaining the desired number of transistors per memory cell.
2Reliability
If the capacitance of the storage device is increased, then the operating parameters of the memory cell are improved, but the area occupied by the memory cell increases
Solution Approach 1:
The patent utilizes vertical stacking to position multiple transistor gates above the storage device, effectively moving the transistor structures into the third dimension. This approach allows increased capacitance in the storage device without proportionally increasing the horizontal area, as the transistor control structures are arranged vertically rather than laterally.
3Productivity
If the dimensions of individual features are reduced, then the integration density is increased, but the manufacturing precision requirements increase
Solution Approach 1:
The patent adopts a vertical three-dimensional architecture where transistor gates are stacked above the storage device. This vertical arrangement allows for increased integration density by utilizing the vertical dimension rather than continuously shrinking horizontal feature dimensions, thereby potentially reducing the stringency of manufacturing precision requirements for lateral feature sizes.
Data Source
AI summary
A microelectronic device includes a first die and a second die vertically overlying and attached to the first die. The first die includes an array region and a peripheral region horizontally neighboring the array region. The array region includes memory cells respectively including a first transistor structure, a second transistor structure horizontally neighboring the first transistor structure, and a storage device vertically underlying and coupled to the first transistor structure and the second transistor structure. The peripheral region includes sub word line driver circuitry. The second die includes sense amplifier regions and a CMOS region horizontally neighboring some of the sense amplifier regions. The sense amplifier regions are within a horizontal area of the array region of the first die and include sense amplifier circuitry. The CMOS region horizontally neighbors some of the sense amplifier regions and includes CMOS circuitry. Related memory devices and electronic systems are also described.