DDR Memory Write Preamble Handling via DQS Domain Counting
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Solution Overview
Problem
The domain crossing problem in DDR5 memory devices arises due to a phase difference between clock (CLK) and data strobe (DQS) signals, which is exacerbated when write commands are issued close together, resulting in an unsuitable time window for resolving this phase difference, leading to incorrect data capture and write operations.
Innovation Solution
The solution involves keeping the start of the write operation entirely within the DQS domain by counting DQS cycles from the successful capture of the first write start, allowing subsequent write commands to be automatically initiated after a proper number of cycles, thereby eliminating the need to resolve phase differences with the CLK domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write commands are issued close together to improve productivity, then the time window for resolving domain crossing is reduced, but this leads to incorrect data capture and write operations
Solution Approach 1:
The patent applies preliminary action by establishing a domain crossing resolution mechanism before write commands are issued. The system pre-configures the timing window and domain crossing handling logic, allowing subsequent write commands to be issued close together without compromising data capture accuracy. This preliminary setup enables high productivity while maintaining reliability.
2Reliability
If a larger time window is provided for domain crossing resolution to improve reliability, then write commands cannot be issued as quickly, but this reduces productivity
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the timing window parameters based on the specific write command conditions. Instead of using a fixed large time window that limits productivity, the system modifies the timing parameters to optimize both reliability and productivity, allowing quick write command issuance while maintaining accurate domain crossing resolution.
3Reliability
If the programmable preamble portion is extended to provide a larger timing window, then data capture reliability is improved, but this increases the time required for write operations
Solution Approach 1:
The patent applies partial action by implementing a streamlined preamble portion that provides just enough timing window for reliable data capture without excessive extension. The system uses a partial preamble approach that maintains sufficient reliability while minimizing the time required for write operations, avoiding the penalty of overly extended preambles.
Data Source
AI summary
A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.