Memory Device Read Disturb Reduction via Line Floating
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Solution Overview
Problem
Resistive memory devices experience read disturb errors due to changes in resistance distribution caused by temperature increases, particularly when word lines and bit lines have high capacitance values, reducing the reliability of read cycles.
Innovation Solution
A memory device design that includes a memory cell array connected to word lines and bit lines, with a control logic circuit to perform pre-charge and floating operations, where one line is floated and the other pseudo-floated during a data read operation, reducing capacitance values and minimizing read disturb errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a current sensing scheme is used to read memory cell data, then data can be sensed by reading voltage variation, but read disturb errors increase when temperature rises significantly
Solution Approach 1:
The patent applies preliminary action by performing pre-charge operations on word lines and bit lines before the actual data sensing operation. The pre-charge period charges the lines to specific voltage levels in advance, which stabilizes the electrical characteristics and reduces temperature-induced resistance distribution changes during the subsequent read operation, thereby preventing read disturb errors
Solution Approach 2:
The patent changes electrical parameters by applying different pre-charge voltages to word lines and bit lines (e.g., Vcc for bit lines, Vss or intermediate voltages for word lines) and controlling the timing duration of these pre-charge operations. This parameter optimization compensates for temperature effects and reduces read disturb while maintaining accurate data sensing
2Quantity of substance
If word lines and bit lines have high capacitance values, then more charge can be stored, but read disturb errors increase and the number of guaranteed read cycles decreases
Solution Approach 1:
The patent performs pre-charge operations before data sensing to establish proper voltage levels on high-capacitance word lines and bit lines. By charging these lines in advance with appropriate voltages, the system reduces the sudden charge/discharge currents that cause read disturb errors, thereby enabling reliable reading even with high capacitance values
Solution Approach 2:
The patent introduces periodic action through the structured timing sequence of pre-charge period followed by sensing period. This periodic operation pattern allows the high-capacitance lines to be properly charged during the pre-charge phase, then stabilized during the sensing phase, reducing read disturb while maintaining charge storage capacity
Data Source
AI summary
The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.